A mismatch-independent DNL pipelined analog-to-digital converter

Abstract

A novel approach for CMOS pipelined analog-to-digital conversion based on switched-capacitor implementation is proposed. This converter's differential nonlinearity (DNL) is independent of any element mismatches in residue amplification. Derivations of the causes on DNL errors in conventional architectures are presented. The DNL of any pipelined converter is dependent upon the conditioning of the residue in the sub-digital-to-analog converter (sub-DAC) and interstage gain stages more than in the choice threshold of the sub-analog-to-digital converter. With well-conditioned residue, any errors made in the sub-DAC's of any earlier stage are evenly distributed over the range of subsequent stages' digital codes. This property is exploited in the design of the proposed converter, which achieves a measured 12 bit resolution and a simulated resolution of 13 bits, even under a 5% mismatch in capacitor ratios. The prototype is implemented using an operational transconductance amplifier with gain boosting. The ADC runs at 10 MHz (3.3 Ms/s).