Switched-capacitor Finite Impulse Response Research Articles

Integrated CMOS GSM baseband channel selecting filters realized using switched capacitor finite impulse response technique

A problem of the design and optimization of analog channel selecting filters, which are needed in wireless communication systems, is considered and evaluated in this paper on an example of the baseband GSM (global system for mobile telephony) channel filter. Two versions of this filter, both designed by the authors using switched-capacitor finite impulse response (SC FIR) technique, are presented and compared to each other as well as to other concurrent designs. In order to fully and plausibly compare the both filter versions (the newer and the elder one), the authors decided to design and fabricate both filters using the same technology, i.e., the technology of the elder filter version, which is the two metal, two poly CYE CMOS 0.8 μm process. The conclusions, which have been drawn, are, however, general and to a large extent technology independent. Although both presented filters are switched-capacitor (SC) finite impulse response (FIR) systems [Dąbrowski A, Cetnarowicz D, Długosz R, Pawłowski P. Design and optimisation of integrated CMOS FIR SC channel filter for a GSM Receiver, European Conference on Circuit Theory and Design, Helsinki, 28–31 August 2001. p I.265; Długosz R, Dąbrowski A, Pawłowski P. Design and measurement results of the GSM SC FIR channel filter realized in CMOS 0.8 μm technology. In: 9th international conference mixed design of integrated circuits and systems, 2002. p. 607–12] they essentially differ to each other as they are based on two quite different SC FIR delay line structures. In the first filter version Gillingham delay elements [Gillingham P. Stray-free switched-capacitor unit delay circuit. Electron lett 1984;20(7):308–10] are used, while in the second version even and odd delay elements [Dąbrowski A. Multirate and multiphase switched-capacitors circuits, London: Chapman & Hall; 1997; Dąbrowski A, Menzi U, Moschytz GS. Design of switched-capacitor FIR filters with application to a low-power MFSK receiver. IEE Proceedings-G 1992;139(4):450] are alternately connected to form the delay line. In this way an interesting comparison of these two SC delay line concepts has been possible. It should also be stressed that the frequency responses of both presented filters have been designed using the same technique, i.e., the Kaiser window of order N = 31. The upper frequency is in both cases equal to 500 kHz and the frequency of the controlling clock generator is equal to 1 MHz. The filter with Gillingham delay elements dissipates 30 mW with the 3 V supply voltage and occupies 2.2 mm 2. On the contrary, the even–odd SC FIR filter dissipates 18 mW only with the 3 V supply voltage and occupies 2.4 mm 2. Moreover, the newer filter version has the stopband attenuation greater by about 10 dB than the previous version.

2D video rate SC FIR filters based on analog RAMs

Monolithic CMOS analog implementations of video systems are extremely attractive because of their low area and power requirements. Switched-capacitor circuits may advantageously replace many current digital solutions of video systems. However, special care must be used in order to handle, with standard CMOS technology, the problems related to the broadband characteristics of video systems. Moreover, two-dimensional (2D) filters require long delay lines, which are not easily implementable in the analog domain. Therefore, new design solutions must be developed, such as the architecture based on analog random-access memories for 2D video-rate switched-capacitor finite-impulse response (FIR) filters, proposed in this work. This structure can be optimized with respect to area requirements and precision requirements, because it allows the exploiting of impulse-response symmetries of linear-phase FIR fitters. The characteristics and the feasibility of the proposed design solution are demonstrated in the design of a 2D low-pass filter for picture-in-picture resizing.

Impulse sampled FIR interpolation with SC active-delayed block polyphase structures

The authors propose new switched-capacitor (SC) active-delayed block (ADB) polyphase structures for analogue finite impulse response (FIR) interpolation. Their system functions are not distorted by the input sample-and-hold filtering effect at the lower input sampling rate. Both canonic and non-canonic ADB polyphase architectures which are superior in terms of a lower speed requirement for OAs, and fewer OAs, respectively, will be proposed for SC FIR interpolators.

Design of switched-capacitor FIR filters with application to a low-power MFSK receiver

Finite impulse response (FIR) switched-capacitor (SC) filters for minimum frequency-shift keying (MFSK) demodulation techniques have been developed and are discussed. The proposed filters comprise combinations of the following building blocks: sample-and-hold circuits, even-odd delay circuits, Gillingham delay circuits, recharge memory elements, Lee-Martin summer circuits, recharge summer circuits, and rotator switches. These are described in the paper. Furthermore, composite SC filter structures are derived using a morphological approach. The FIR SC filter structures are compared and evaluated with respect to the required chip area when implemented in 3 μm CMOS technology, and, by computer simulation, with regard to bit error probability when used in an MFSK receiver. It is shown that the receiver performance is independent of the FIR filter structure used. Furthermore, using the FIR filters, and for a given bit error probability, the required signal-to-noise ratio (SNR) is actually 3 dB lower than for a typical commercial MFSK receiver (e.g. an MB87002).

Systematic method for the design of multiamplifier switched-capacitor FIR decimator circuits

The paper presents a systematic method for the design of multiamplifier switched-capacitor (SC) decimator circuits with finite impulse response (FIR) transfer functions. From a formal description of previously proposed architectures, a set of closed form equations are derived to determine the resulting capacitance values in the circuits as a function of the desired impulse response coefficients and signal handling capability. The systematic design of two multiamplifier FIR SC decimators is then illustrated considering the practical example of an application suitable for video signal processing.