Switched-capacitor Circuits Research Articles

New tactile sensor chip with silicone rubber cover

We report on a new tactile sensor chip developed for measuring distribution of forces on its surface. The chip has eight force-sensitive areas, called “taxel” with a pitch of 240 μm. Surface micromachining techniques are used to produce small cavities that work as pressure-sensitive capacitors. The process is CMOS compatible, therefore, on-chip switched capacitor circuits can be used for signal amplification. To enable transduction of normal forces to the sensitive areas, we cover the sensor chip surface with silicone rubber. First, measurements show that the sensor's output can be explained by results from contact mechanics. We demonstrate this by the simple case of a hard sphere pressed in the silicone rubber cover. The center of contact can be measured within 2 μm precision. The radius of the sphere and the load working on it can be estimated with high precision from the tactile sensor output data.

DFT for digital detection of analog parametric faults in SC filters

Parametric faults are a significant cause of incorrect operation in analog circuits. Many design for test techniques for analog circuits are ineffective at detecting multiple parametric faults because either their accuracy is poor, or the circuit is not tested in the configuration in which it is used. We present a design for test (DFT) scheme that offers the accuracy needed to test high-quality circuits. The DFT scheme is based on a circuit that digitally measures the ratio of a pair of capacitors. The circuit is used to characterize the transfer function of a switched capacitor circuit, which is usually determined by capacitor ratios. In our DFT scheme, capacitor ratios can be measured to within 0.01% accuracy and filter parameters can be shown to be satisfied to within 0.1% accuracy. With this characterization process, a filter can be directly shown to satisfy all specifications that depend on capacitor ratios. We believe the accuracy of our approach is at least an order of magnitude greater than that offered by any other DFT scheme reported in the literature.

Time-domain thermal noise simulation of switched capacitor circuits and delta-sigma modulators

This paper presents an accurate and efficient algorithm for simulating the effects of thermal noise in time-domain. The algorithm presented in this paper is based on Monte Carlo methods and is applicable to linear time invariant circuits. In addition to linear time invariant elements, the algorithm can easily be extended to include clock controlled switches and single or multibit quantizers. This expands the thermal noise analysis capability to switched capacitor circuits and oversampled delta-sigma modulators. Thermal noise generated by different elements is modeled, in the time-domain, by a random pulse waveform having a desired power spectral density. Typically the noise power level is much smaller than that of other desired signals in the circuit and accurate simulation is needed to obtain correct results. In addition, random noise waveforms require the computation of many time points in each transient analysis and efficient simulation methods are needed. In this paper, a new method for computing the transient response of linear time invariant circuits is used. This method accurately and efficiently computes the response to the random pulse waveforms. In addition to thermal noise, the method can also be used to simulate the effect of random dither signals in delta-sigma modulators. Examples of noise simulation are given and, when possible, comparison with measurements, previously published results, or analytical expressions is done.

Low-Power Area-Efficient Pipelined A/D Converter Design Using a Single-Ended Amplifier

This paper presents a new scheme of a low-power area-efficient pipelined A/D converter using a single-ended amplifier. The proposed multiply-by-two single-ended amplifier using switched capacitor circuits has smaller DC bias current compared to the conventional fully-differential scheme, and has a small capacitor mismatch sensitivity, allowing us to use a smaller capacitance. The simple high-gain dynamic-biased regulated cascode amplifier also has an excellent switching response. These properties lead to the low-power area-efficient design of high-speed A/D converters. The estimated power dissipation of the 10-b pipelined A/D converter is less than 12 mW at 20 MSample/s.

An intelligent pressure sensor using neural networks

In this paper, we propose a scheme of an intelligent capacitive pressure sensor (CPS) using an artificial neural network (ANN). A switched-capacitor circuit (SCC) converts the change in capacitance of the pressure-sensor into an equivalent voltage. The effect of change in environmental conditions on the CPS and subsequently upon the output of the SCC is nonlinear in nature. Especially, change in ambient temperature causes response characteristics of the CPS to become highly nonlinear, and complex signal processing may be required to obtain correct readout. The proposed ANN-based scheme incorporates intelligence into the sensor. It is revealed from the simulation studies that this CPS model can provide correct pressure readout within /spl plusmn/1% error (full scale) over a range of temperature variations from -20/spl deg/C to 70/spl deg/C. Two ANN schemes, direct modeling and inverse modeling of a CPS, are reported. The former modeling technique enables an estimate of the nonlinear sensor characteristics, whereas the latter technique estimates the applied pressure which is used for direct digital readout. When there is a change in ambient temperature, the ANN automatically compensates for this change based on the distributive information stored in its weights.

CMOS switched-op-amp-based sample-and-hold circuit

This paper presents a sample-and-hold design that is based on a switched-op-amp topology. Charge injection errors are greatly reduced by turning off transistors in the saturation region instead of the triode region as is the case for traditional MOS switches. The remaining clock feed through error is mostly signal-independent and is cancelled out by a pseudodifferential topology. Switched-opamps are designed and fabricated in a 2-/spl mu/ CMOS technology. The measurement results show that the harmonics are at least 78 dB below the signal level. Both the measurement results from fabricated ICs and simulation results suggest the potential benefits of this approach in comparison to traditional switched-capacitor circuits.

Improved switched-capacitor interpolators with reduced sample-and-hold effects

This paper proposes improved switched-capacitor (SC) interpolators using a novel sampling technique which eliminates the undesired distortion due to the sample-and-hold shaping effect at the lower input sampling rate. Such a sampling technique not only leads to a precise analog interpolation, as its digital counterpart does, but also allows to simplify the design procedures and resulting SC circuit implementations. Different circuit topologies with both finite- and infinite-impulse response characteristics are developed, respectively, for low- and high-selectivity filtering. Practical implementation issues are discussed with respect to capacitance ratio mismatches, as well as finite gain, bandwidth, and offset sensitivity effects of operational amplifiers. Besides detailed computer-based analyses, experimental results obtained from discrete component prototypes are also presented to demonstrate the proposed circuits.

Programmable Switched Capacitor Circuits

Phase locked loops (PLLs) are finding a wide range of applications in signal processing because of its availability in monolithic form. In this paper, we present some applications of PLL in switched capacitor circuits. In particular, programmable gain SC amplifier, programmable frequency independent SC phase shifter and SC oscillator have been suggested. The programmability in these circuits is obtained by varying the clock signal with the help of PLL and programmable frequency divider. The experimental results match well with the theoretical predictions.

A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL applications

The design of a high-resolution, high-speed, delta-sigma analog to-digital converter that operates from a single 3.3-V supply is presented. This supply voltage presents several design problems, such as reduced signal swing and nonzero switch resistance in the switched-capacitor circuits. These problems are tackled in this design by a careful optimization at the system level and by a detailed analysis of several circuit nonidealities. The converter uses a 2-1-1 cascade topology with optimized coefficients. For an oversampling-ratio of only 24, the converter achieves a signal-to-noise ratio of 87 dB, a signal-to-(noise+distortion) ratio of 82 dB, and an input dynamic range of 15 bits after comb filtering. The converter is sampled at 52.8 MHz, which results in the required signal bandwidth for asymmetrical digital subscriber line applications of 1.1 MHz. It is implemented in a 0.5-/spl mu/m CMOS technology, in a 5-mm/sup 2/ die area, and consumes 200 mW from a 3.3-V power supply.

A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology

This paper presents a CMOS 0.7-/spl mu/m /spl Sigma//spl Delta/ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16. It uses fully differential switched-capacitor circuits with a clock frequency of 35.2 MHz, and has a power consumption of 55 mW. Such a low oversampling ratio has been achieved through the combined usage of fourth-order filtering and multibit quantization. To guarantee stable operation for any input signal and/or initial condition, the fourth order shaping function has been realized using a cascade architecture with three stages; the first stage is a second-order modulator, while the others are first-order modulators-referred to as a 2-1-1/sub mb/ architecture. The quantizer of the last stage is 3 bits, while the other quantizers are single bit. The modulator architecture and coefficients have been optimized for reduced sensitivity to the errors in the 3-bit quantization process. Specifically, the 3-bit digital-to-analog converter tolerates 2.8% FS nonlinearity without significant degradation of the modulator performance. This makes the use of digital calibration unnecessary, which is a key point for reduced power consumption. We show that, for a given oversampling ratio and in the presence of 0.5% mismatch, the proposed modulator obtains a larger signal-to-noise-plus-distortion ratio than previous multibit cascade architectures. On the other hand, as compared to a 2.1.1/sub single-bit/ modulator previously designed for a mixed-signal asymmetrical digital subscriber line modem in the same technology, the modulator in this paper obtains one more bit resolution, enhances the operating frequency by a factor of two, and reduces the power consumption by a factor of four.

MOSFET-only switched-capacitor circuits in digital CMOS technology

Design techniques are described for the realization of precision high linearity switched-capacitor (SC) stages constructed entirely from MOS transistors. The proposed circuits use the gate-to-channel capacitance of MOSFET's for realizing all capacitors. As a result, they can be fabricated in any inexpensive basic digital CMOS technology, and the chip area occupied by the capacitors can be reduced. A number of different SC stages have been designed and fabricated using the proposed techniques. These included SC amplifiers, gain/loss stages, and data converters. Both the simulations and the experimental results obtained indicate that very high linearity (comparable to that achieved using analog fabrication processes with two poly-Si layers) can be achieved in these circuits using basic CMOS technology.

Very low-distortion fully differential switched-current memory cell

This paper proposes a very low-distortion fully differential switched-current memory cell, based on the opening of the memory switch at a constant voltage. We show that in the previously proposed single-ended Nairn cell, this principle does not lead to low harmonic distortion because the distortion is also a function of the signal-independent clock injection. SPICE simulations indicate that the proposed cell achieves a distortion level of -90 dB to -100 dB, which is about two orders of magnitude below the level achieved with basic switched-current cells. The performance of the proposed cell is near that of state-of-the-art switched-capacitor circuits.

Bandpass sigma-delta modulation using frequency translation

A bandpass sigma-delta modulation Analog-to-Digital (A/D) converter that uses direct conversion to base-band with in phase and quadrature paths within the feedback loop is described. The bandpass input signal is processed with continuous-time circuitry and the I/Q base-band signals are processed with switched-capacitor circuits. Experimental and simulation results indicate that the passband center frequency can be maximized while suppressing the effects of I/Q mismatches.

2D video rate SC FIR filters based on analog RAMs

Monolithic CMOS analog implementations of video systems are extremely attractive because of their low area and power requirements. Switched-capacitor circuits may advantageously replace many current digital solutions of video systems. However, special care must be used in order to handle, with standard CMOS technology, the problems related to the broadband characteristics of video systems. Moreover, two-dimensional (2D) filters require long delay lines, which are not easily implementable in the analog domain. Therefore, new design solutions must be developed, such as the architecture based on analog random-access memories for 2D video-rate switched-capacitor finite-impulse response (FIR) filters, proposed in this work. This structure can be optimized with respect to area requirements and precision requirements, because it allows the exploiting of impulse-response symmetries of linear-phase FIR fitters. The characteristics and the feasibility of the proposed design solution are demonstrated in the design of a 2D low-pass filter for picture-in-picture resizing.

Automatic symbolic analysis of SC networks using a modified nodal approach

This paper presents a symbolic analysis of Switched-Capacitor (SC) circuits in the z-domain using Modified Nodal Approach (MNA). We have selected the MNA method as one of the widely established approaches in circuit analysis. The analyses are performed using SymsimC symbolic simulator which also enables s-domain network analysis. Macromodels of various SC-basic building blocks are utilized to decrease the number of equations describing the circuit which in turn relaxes the analysis. The results of simulations are demonstrated on a benchmark example of an SC-network that was frequently used in previous papers. The new feature imposed with this work is the examination of the influence of finite gain and bandwidth of operational amplifiers on the circuit's behaviour. The obtained results could serve as a valuable aid to the designer in the assessment of designed circuit performance.

A 15-b resolution 2-MHz Nyquist rate ΔΣ ADC in a 1-μm CMOS technology

A high-resolution high-speed fourth-order cascaded /spl Delta//spl Sigma/ analog-to-digital converter, based on a 2-1-1 topology, is presented. The converter is implemented with fully differential switched capacitor circuits in a standard 1-/spl mu/m CMOS technology. The converter uses two symmetrical reference voltages of 1 V, and is driven by a single 48-MHz clock signal. With an oversampling ratio of only 24, the converter achieves a resolution of 91 dB, a peak SNR of 90 dB, and a peak SNDR of 85 dB at a Nyquist rate of 2 MHz after comb filtering. The power consumption of the converter is 230 mW, from a single 5-V supply voltage.

A switched-current, switched-capacitor temperature sensor in 0.6-μm CMOS

A temperature-to-digital converter is described which uses a sensor based on the principle of accurately scaled currents in the parasitic substrate p-n-p in a standard fine-line CMOS process. The resulting PTAT /spl delta/V/sub BE/ signal is amplified in an auto-zeroed switched-capacitor circuit, sampled, and converted to a digital output by a low-power 10-bit SAR ADC providing a resolution of 0.25/spl deg/ from -55/spl deg/C to 125/spl deg/C with an error of less than 1/spl deg/. A single adjustment of temperature error is provided for wafer probe. No further calibration is required. A switching bandgap reference circuit will also be described which uses similar techniques to generate an accurate low-noise reference voltage for the ADC. The circuits are part of a multichannel data-acquisition system where other input voltages must also be sampled and measured, and so the speed and power of the ADC is not determined by the temperature sensor alone. For continuous operation, the supply current is 1 mA, but a low-power mode is provided where the part is normally in shut down and only powers up when required. In this mode, the average power supply current at 10 conversions/s is 0.3 /spl mu/A. The supply voltage is 2.7-5.5 V.

ANN-based intelligent pressure sensor in noisy environment

A novel artificial neural network (ANN)-based intelligent capacitive pressure sensor (CPS) in noisy environment is proposed in this paper. A switched capacitor circuit (SCC) is used to convert the change in capacitance of the CPS due to applied pressure into a proportional voltage which is then applied to the ANN model to estimate the pressure. Because of the nonlinear response characteristics of the CPS and its temperature dependence, complex signal processing of the SCC output is required to estimate the applied pressure accurately, especially when the room temperature changes with time, place, or both. The situation becomes further complicated when the CPS encounters random noise, as is the case in many practical situations. To alleviate these difficulties in estimation of unknown applied pressure in a CPS, a multilayer perceptron (MLP) has been utilized to model the CPS characteristics over a wide temperature range with noise. By training the MLP model suitably, a direct digital readout of the applied pressure can be obtained. From the simulation studies it was verified that the performance of this model is quite satisfactory for a wide variation of temperature, starting from −20°C to 70°C, and for a signal-to-noise ratio (SNR) of 40 dB and above. This modeling technique provides greater flexibility and accuracy in a changing and noisy environment.

Direct analysis and synthesis of multiphase switched-current networks using signal-flow graphs

A by-inspection analysis and synthesis method for multiphase switched-current (SI) circuits using signal-flow graph (SFG) techniques is presented. The SFG is derived on the transistor level and the method is primarily useful for the hand analysis and design of small and medium-size SI circuits (e.g. SI filters, decimators, interpolators). Tables of commonly used SI circuits, in which the corresponding SFGs and circuits are given, make the derivation easy and fast. From the SFGs, not only the overall discrete-time transfer function, but also those in-between individual switching phases, are obtainable. With the proposed method it is straightforward to include non-ideal effects, such as finite output resistance of MOS transistors, clock-feedthrough and settling error. The method is also a useful tool for the synthesis of new SI circuits. It is shown that every low-sensitivity switched-capacitor (SC) circuit can be mapped directly into a low-sensitivity SI circuit with a corresponding topology. Examples of transformed SC circuits are given and two new double sampling integrators are introduced. © 1998 John Wiley & Sons, Ltd.

Switched-capacitor inverter with high power density and enhanced regulation capability

A DC-AC inverter containing no inductors or transformers is presented. The role of the magnetic devices is played by a switched-capacitor (SC) circuit, formed by two subcircuits. Each SC-subcircuit contains 15 basic cells, each one formed by one capacitor, two MOSFETs and two diodes. The sinusoidal output waveform is realized in a staircase, formed by 64 steps. To achieve each step, the inverter operates like a step-up DC-DC converter: by using a certain number of SC-cells, the input voltage is boosted to the voltage required by the step in consideration. Each step is implemented in a large number of switching cycles. In each cycle, the inverter goes through four phases; according to a designed switching sequence, some of the capacitors of the SC-cells involved in the respective step are in a charging process from line, while the others are in a discharging process to the load. The phases 2 and 4 have a regulation role only. A duty cycle control is used. A Fourier analysis evidences the clean AC output waveform. The inverter exhibits low weight, high power density, and enhanced regulation for large changes in line and load.