Switch Matrices Research Articles

Recent Developments in Polymer-Based Photonic Components for Disruptive Capacity Upgrade in Data Centers

Recently developed photonic components for next-generation datacenter systems based on the Heinrich Hertz Institute´s PolyBoard integration platform are reviewed. Hybrid-integrated transmitters and receivers, including optical functionalities, such as tunable lasers, polarization manipulators, 1 × 2 switches, and variable optical attenuators, are presented. The flexibility of those devices provides the possibility of generating, routing and detecting multiple optical data flows, offering the potential of aggregating traffics of 1 Tb/s and beyond. In addition, vertically stacked polymer waveguide structures are presented, opening the way towards the third dimension in photonic integration and allowing increasing the transmission capacity beyond the physical limit of standard single mode fibers. The freedom in the arrangement of the polymer waveguides allow for the matching of different multicore fiber types, providing the possibility of processing in parallel the different optical flows. By means of micromachining 45 $^{\circ}$ mirrors on the different stack levels, the three-dimensional (3-D) stacked waveguide structure can act as an interface between multicore fibers and planar optoelectronic devices such as photodiodes and laser diodes. Furthermore, a novel concept for a 4 × 4 3-D optical switch based on 3-D multimode interferometers is presented and numerically proven, showing potential for its application as the interface between multicore fibers and planar optoelectronic devices, as well as offering the possibility of reconfigurable N × N switching matrices.

Integrated analogue–digital control circuit for photonic switch matrices

An analogue–digital circuit for thermal control of the resonance frequency of optical ring resonators is suggested. This approach is characterised by a low power dissipation of 209 µW and needs only 2800 µm2 of chip area in 0.16 µm CMOS technology. Therefore, it is well appropriate to be used to control each of the cells of large optical switch matrices. Compared with a purely analogue heater control approach the power dissipation is reduced to 7%.

In brief

PAGE 1022 Researchers from the Institute of Image Processing and Pattern Recognition propose a simple algorithm with robust performance. It provides powerful image and video detail enhancement and is particularly useful for practical applications, being easily hardware implemented in field-programmable gate arrays. PAGE 1060 A team from the University of Nantes in France present an accurate model-based method for estimating the position of targets, using a bistatic MIMO radar system. They used factor analysis to estimate components and to precisely locate the targets in terms of Cartesian coordinates. The final enhanced images and videos tend to be more visible and natural looking PAGE 996 Collaboration between the Technical University of Denmark and Chungnam National University in Korea has produced a new circuit layout that enables precise matching of reactive values in small electric and magnetic spherical dipole antennas. The experimental results verified those of the circuit and electromagnetic simulations. GPR and indoor localisation are some typical applications of near field source localisation PAGE 1054 An integrated balancing transformer for a high frequency parallel AC-LED drive circuit is proposed. The team from Gyeongsang National University designed and implemented the transformer, with the experimental results showing the operation and current balancing performance of the proposed scheme. It is expected that the proposed technique will prove useful for high power AC-LED applications. The results of this work can be effectively used in the engineering fields that require small magnetic antennas with wide-band operation PAGE 1045 A team from the Vienna University of Technology suggest an analogue-digital circuit for thermal control of the resonance frequency of optical ring resonators. Compared to a purely analogue heater control, the approach dissipates 7% less power. The approach is appropriate for controlling the individual cells of large optical switch matrices. The engineering application of this work includes high powered LED lighting applications The approach has been successfully verified with a test chip and is very important for the advancement of electronic-photonic integration

Integrated optical switch matrices for packet data networks.

Integrated circuit technologies are enabling intelligent, chip-based, optical packet switch matrices. Rapid real-time re-configurability at the photonic layer using integrated circuit technologies is expected to enable cost-effective, energy-efficient, and transparent data communications. InP integrated photonic circuits offer high-performance amplifiers, switches, modulators, detectors, and de/multiplexers in the same wafer-scale processes. The complexity of these circuits has been transformed as the process technologies have matured, enabling component counts to increase to many hundreds per chip. Active–passive monolithic integration has enabled switching matrices with up to 480 components, connecting 16 inputs to 16 outputs. Integrated switching matrices route data streams of hundreds of gigabits per second. Multi-path and packet time-scale switching have been demonstrated in the laboratory to route between multiple fibre connections. Wavelength-granularity routing and monitoring is realised inside the chip. In this paper, we review the current status in InP integrated photonics for optical switch matrices, paying particular attention to the additional on-chip functions that become feasible with active component integration. We highlight the opportunities for introducing intelligence at the physical layer and explore the requirements and opportunities for cost-effective, scalable switching.

Integrated Pulsewidth Modulation Control for a Scalable Optical Switch Matrix

A scalable pulsewidth control approach with 7-bit resolution for thermal control of optical ring resonator switch matrices in 0.16- $\mu\text{m}$ Bipolar-CMOS-DMOS (BCD) with a cell size of $79\ast 105 \mu\text{m}^2$ is introduced. One Gray counter at up to 1.2-GHz clock and pulsewidth modulation generation in each matrix cell leads to an electrical power consumption of 330 mW for all electronic control circuits of an optical 1000-switch-node matrix, resulting in a reduction of 11.1% of the power needed by a constant-voltage control approach.

Performance improvement of a reconfigurable series-shunt switch via asymmetric structure based RF-MEMS capacitive switch

This paper presents a series combination of metal to metal contact and capacitive RF-MEMS switches for multi-band wireless applications. For performance improvement a novel capacitive shunt switch is used and the response has been compared with a conventional shunt device. The proposed design shows the insertion loss better than 0.35 dB and return loss below 13.96 dB up to 30 GHz as compared to 1.64 dB insertion loss and 6.14 dB of return loss with conventional device. Isolation peaks of 75.33, 71.58 and 72.98 dB has been observed at 8.2, 7.3 and 15.5 GHz when left, right or both cantilevers are electro-statically actuated in the down-state respectively, whereas conventional device has peak only at 7.3 GHz. Further, a reduction of about 60 % in the pull-in voltage of capacitive switch and 17.5 % in device area has also been observed. The proposed design can be used as a building block for multiple throw switches and switch matrices for the future reconfigurable RF front end applications.

Dynamic scrambling scheme of arrayed-waveguide grating-based encryptors and decryptors for protection against eavesdropping

To enhance confidentiality and reduce the number of arrayed-waveguide grating (AWG) routers, a dynamic scrambling scheme is proposed in which cyclic and free spectral range (FSR) properties of AWG routers are employed to use a maximal-length sequence (M-sequence) code as the signature address code. In this paper, a changing codeword mechanism is presented in which a flexible dynamic scrambling algorithm is embedded in the encoding and decoding codebook to control the state of both the wavelength and spatial optical (or electrical) switch matrices. Hence, the code family and code changing flexibility of the proposed scheme increases substantially because of the multiple effects of the wavelength and spatial switch matrices. Compared with the existing dynamic reconfigurable AWG-based schemes without multiple changing codewords in the FSR groups and spatial domains, the confidentiality of the proposed scheme is approximately 104 times higher than that of schemes without scrambling codeword mechanisms.

Design and Performance of a Cyclic Fault-Tolerant Semiconductor Optical Amplifier Switch Matrix

We propose a cyclic fault-tolerant structure for a semiconductor optical amplifier (SOA) switch matrix in a tree arrangement by connecting the inputs of the switch matrix into a ring with additional SOAs. Upon component failures, the affected requests are rerouted through their neighboring inputs toward the desired outputs. By making use of the existing components while rerouting, the proposed structure achieves an excellent trade-off between the number of additional components, hence size and cost, and fault tolerance. Numerical simulations show that under 210 randomly distributed SOA failures in a 32 × 32 switch matrix, the proposed structure is still able to provide more than 99% connectivity between all input-output port pairs. We also show through simulations that the proposed structure could potentially scale up to large port counts by limiting the length of the rerouted paths. And its fault-tolerance capability improves as the size of the switch matrix increases. Experiments are conducted to verify the feasibility of the proposed structure. Our research provides clues to improve the fault tolerance of some kinds of switch matrices, where rerouting within the switch matrix itself is not possible, such as single-stage matrices.

Cost evolution model to design optical switching fabrics with wavelength converters

Optical switching is expected to provide high degree of flexibility in future Internet networking. Exploitation of sub-wavelength domain based on emerging optical technology is attractive from a functional and performance perspective but its feasibility must be proven also in relation to the costs of components. In this paper a new methodology to compare optical switching matrices based on different wavelength converters sharing strategies is presented, which introduces component cost evolution in time. The methodology is applied to compare different switch configurations by taking into account possible evolution in component costs relationship in relation to technology availability. Design guidelines are drawn based on extensive simulations.

RF MEMS for Reconfigurable RF Front-End: Research in Australia

This paper reviews some ground breaking development of RF MEMS technology in Australia at the UNSW, over the past decade. It presents some unique and novel designs using RF MEMS switches to achieve reconfigurable RF front-end circuits. These designs include multiport RF MEMS switches, switch matrices, reconfigurable filters and antennas. The resulting devices achieved RF performance that is unmatched by any existing RF andmicrowave technologies.

Comparison of Signal Switching Matrices for Remote Laboratories and a Novel Solution Using FPGA Technology

The concept of signal switching matrices in the field of remote laboratory systems is presented in this paper. Existing solutions for this problem are reviewed and a novel approach using FPGA technology is proposed. The FPGA implementation method is described in details and compared to the existing solutions in terms of implementation costs, surface requirements, universality, and feasibility. It is shown that the novel approach using FPGA technology for the implementation of signal switching matrices stands as the most desirable solution for this purpose.

Series Reversion Solution for MIMO Microwave Feed Networks

A solution based on series reversion is derived and tested to estimate an N-port device-under-test (DUT) scattering matrix through a multiple-in/multiple-out microwave feed network. The feed network uses power dividers in place of fan-in/fan-out stages of traditional double-pole N-throw (2PNT) switching matrices. A fast recursive algorithm is derived to simultaneously estimate the DUT scattering matrix and solve the multiple scattering problem for weakly interacting networks. In experiment, the method was able to recover the scattering matrix of a passive DUT to within 0.1 dB in magnitude and 2° in phase.

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Design of RF MEMS based switch matrix for space applications

Abstract. RF MEMS based switch matrices have several advantages compared to the mechanical or solid-state switch based ones for space applications. They are compact, light and less lossy with a high linearity up to high frequency. In this work, a 12 × 12 switch matrix with RF MEMS and LTCC technologies is presented based on the planar Beneš network. The simulated performance of the 12 × 12 switch matrix is below −12 dB IL (Insertion Loss) up to C band and −15 dB RL (Return Loss) up to Ku band. Moreover, it has a good isolation better than −50 dB. A 4 × 4 switch matrix with the same design process and technologies is fabricated and measured to verify the 12 × 12 switch matrix design process. The measured performance agrees very well to the simulations.

Fuzzy dissipative control for nonlinear Markovian jump systems via retarded feedback

This paper deals with the problem of the dissipative control for a class of nonlinear Markovian jump systems through Takagi–Sugeno fuzzy model approach. The transition rates of Markovian process under consideration are assumed to be partly known. We aim to design retarded feedback controllers such that the resulting closed-loop system is stochastically stable and strictly (Q,S,R)-θ-dissipative. By introducing a novel augmented Lyapunov functional and some free Markovian switching matrices, some sufficient conditions for the solvability of the above problem are given in terms of linear matrix inequalities. Finally, two numerical examples are given to demonstrate the effectiveness of our proposed approach.

Novel Miniaturized RF MEMS Staircase Switch Matrix

A novel implementation of wideband large switch matrices is proposed in this letter. The solution is based on staircase geometry. The approach demonstrates significant reduction in the number of control signal required compared to all existing RF MEMS switch matrix geometries, while maintaining the performance. This letter presents the design and characteristics of a semi-T switch cell and a 3 t 3 staircase switch matrix. The measurement of the switch matrix demonstrated excellent RF performance of maximum insertion loss of 2 dB, a return loss of better than 15 dB and an isolation higher than 40 dB for frequencies up to 40 GHz. To our knowledge, this is the first RF MEMS staircase switch matrix ever reported.

Run-time generation of partial FPGA configurations for subword operations

Instructions for concurrent processing of smaller data units than whole CPU words are useful in areas like multimedia processing and cryptography. Since the processors used in FPGA-based embedded systems lack support for such applications, this paper proposes mapping sequences of subword operations to a set of hardware components and generating the corresponding FPGA partial configurations at run-time. The technique is aimed at adaptive embedded systems that employ run-time reconfiguration to achieve high flexibility and performance. New partial configurations for circuits implementing sets of subword operations are created by merging together the relocated partial configurations of the hardware components (from a predefined library), and the configurations of the switch matrices used for the connections between the components. The paper presents and discusses results obtained for a 300MHz PowerPC CPU in a Virtex-II Pro platform FPGA. For the set of benchmarks analyzed, the complete configuration creation process takes between 1s and 24s. The run-time generated hardware versions achieve speed-ups between 11 and 73 over the software versions.

Oxygen Ion Drift‐Induced Complementary Resistive Switching in Homo TiOx/TiOy/TiOx and Hetero TiOx/TiON/TiOx Triple Multilayer Frameworks

AbstractDeveloping a means by which to compete with commonly used Si‐based memory devices represents an important challenge for the realization of future three‐dimensionally stacked crossbar‐array memory devices with multifunctionality. Therefore, oxide‐based resistance switching memory (ReRAM), with its associated phenomena of oxygen ion drifts under a bias, is becoming increasingly important for use in nanoscalable crossbar arrays with an ideal memory cell size due to its simple metal–insulator–metal structure and low switching current of 10–100 μA. However, in a crossbar array geometry, one single memory element defined by the cross‐point of word and bit lines is highly susceptible to unintended leakage current due to parasitic paths around neighboring cells when no selective devices such as diodes or transistors are used. Therefore, the effective complementary resistive switching (CRS) features in all Ti‐oxide‐based triple layered homo Pt/TiOx/TiOy/TiOx/Pt and hetero Pt/TiOx/TiON/TiOx/Pt geometries as alternative resistive switching matrices are reported. The possible resistive switching nature of the novel triple matrices is also discussed together with their electrical and structural properties. The ability to eliminate both an external resistor for efficient CRS operation and a metallic Pt middle electrode for further cost‐effective scalability will accelerate progress toward the realization of cross‐bar ReRAM in this framework.

Generalized Multiport Waveguide Switches Based on Multiple Short-Circuit Loads in Power-Divider Junctions

This paper presents a new concept for multiport waveguide switches based on short-circuit loads integrated in power-divider ridge-waveguide junctions. The switching is achieved by means of actuating short and open circuit loads in the waveguide path of a ridge waveguide, eliminating the need of bulky rotors, which are typically used in conventional waveguide switches. A complete class of single-pole N -throw switches (N up to 4) is presented based on this concept. Furthermore, the concept is employed to demonstrate highly compact C-, R-, and T-type waveguide switches by integrating different power-divider junctions in a seamless manner. The T-type case involves three states that provide the maximum flexibility for realizing advanced switch matrices for signal routing. A T-type waveguide switch is built and measured for validating the concept. To our knowledge, this paper marks the first time R- and T-type waveguide switches are demonstrated without the need to use a bulky rotary junction.

Run-time generation of partial FPGA configurations

This paper presents and evaluates a method of generating partial bitstreams at run-time for dynamic reconfiguration of sections of an FPGA. The method is intended for use in adaptive embedded systems that employ run-time reconfiguration to achieve high flexibility and performance. The proposed approach combines partial bitstreams of coarse-grained components to produce a new partial bitstream implementing a given circuit netlist. Topological sorting of the netlist is used to determine the initial positions of individual components, whose placement is then improved by simulated annealing. Connection routing is done by a breadth-first search of the reconfigurable area based on a simplified resource model of the reconfigurable fabric. The desired partial bitstream is constructed by merging together the default bitstream of the reconfigurable area, the relocated partial bitstreams of the components, and the configurations of the switch matrices used for routing. The approach is embodied in a code library that applications can use to create new bitstreams at run-time. For the members of a set of 29 benchmarks (both synthetic and application-derived) having between five and 41 components, the complete process of bitstream generation takes between 8 s and 35 s when running on an embedded PowerPC 405 microprocessor clocked at 300 MHz.