Switch-level Fault Simulation Research Articles

FX: a fast approximate fault simulator for the switch-level using VHDL

Switch-level faults, as opposed to traditional gate-level faults, can more accurately model physical failures found in an integrated circuit. However, one problem with switch-level fault simulation is that of long simulation times. This paper addresses this problem by performing fast approximate switch-level fault simulation using transistor reverse level ordering, and a novel nine-valued switch-level extension to observability. The probability of propagation of a fault from an arbitrary line of the switch-level circuit to the primary output is shown to be a function of the average node fan-in and the line's distance to primary output. Using this probability, results show one order of magnitude of complexity speed-up as compared to traditional fault simulation techniques, while maintaining good accuracy.

Switch-level Differential Fault Simulation of MOS VLSI Circuits

A new switch-level fault simulation method for MOS circuits is presented that combines compiled switch-level simulation techniques and functional fault modeling of transistor faults with the new fault simulation algorithm of differential fault simulation. The fault simulator models both node stuck-at-0, stuck-at-1 faults and transistor stuck-on, stuck-open faults. Prior to simulation, the switch-level circuit components are compiled into functional models. The effect of transistor faults on the function of the circuit components is modeled by functional fault models that execute very fast during simulation. Every compiled circuit component is assigned a dominance attribute, which abstracts relative strength information in the circuit. Dominance is used during simulation to resolve the X-state due to fighting pull-up and pull-down transistor paths and also to deduce transistor fault detectability and fault equivalencies prior to simulation. The differential fault simulation algorithm developed for gate-level circuits is adapted for use at the switch-level. Differential fault simulation provides excellent performance with minimum memory requirements, although it incurs a higher overhead at the switch-level than at the gate-level due to the dynamic memory properties of MOS circuits.

Fault simulation in CMOS VLSI circuits

In digital complementary metal-oxide semiconductor (CMOS) very large-scale integration (VLSI) circuits, physical faults, such as transistor stuck-closed, floating line faults and bridging faults (which include gate-to-drain shorts) cause complex analogue behaviour of the digital circuit. Some of these faults create an intermediate voltage level, which classical switch-level fault simulator techniques are unable to interpret. A general fault simulator is proposed which employs a new technique for evaluating the faulty subcircuit based on analysis of a nonlinear resistive circuit. The technique can be considered an extension of classical switch-level level fault simulators, in which most of the possible physical faults are considered. >