Switch Configuration Research Articles

Low-voltage and compact polymeric optical switches using a Mach–Zehnder interferometer and N side-coupled electro-optic microrings

Universal structure and thorough analysis were proposed for a kind of polymer optical switch using N-th order microring resonator side-coupled Mach–Zehnder interferometer (MRR-SC-MZI). Formulation and expression of output power, insertion loss and crosstalk were derived, and detailed design and optimization were carried out. Analytical results indicate that all devices for N≥1 can perform normal switching function, and 8≥N≥2 is preferred for dropping the driving voltage below 5V. For the seven MRR-SC-MZI EO switches (N=2–8) whose cross-state voltages are within 0–2.32V, their bar-state voltages are within 0.96–4.83V and their insertion losses are within 0.35–0.85dB at bar state, whereas those within 0.14–1.70dB at cross state; their crosstalk are within −20.79 to −31.11dB at bar state, whereas those are within −13.86 to −20.36dB at cross state; their 3-dB electrical bandwidths are within 18.5–28.0GHz, and 3-dB optical bandwidths for the two output ports are within 18.1–40.0GHz and 32.0~55GHz, respectively. Comparison indicates that the driving voltages of the proposed MRR-SC-MZI switching devices are 10–250 times smaller than those of the traditional MZI EO switches with the same EO region length, device length and structural parameters. Therefore, due to small footprint size and low driving voltage, this switching configuration can be densely integrated onto optoelectronic chips.

Line-to-line Voltage Space Vector Modulation for Neutral-point Clamped Multi-level Converter with DC-link Capacitor Voltage Balancing Using Redundant Vectors

This article presents space vector modulation of line-to-line voltage for the three-phase neutral-point clamped n-level converter with DC-link capacitor voltage balancing using redundant vectors. The developed modulation strategy is based on an equivalent matrix structure of the neutral-point clamped n-level converter. The relation between the 3 × (n – 1) switching functions of the matrix converter and gate signals of transistors of the neutral-point clamped n-level converter is given. A line-to-line space vector modulation strategy for a matrix inverter is used to obtain the switching function. For one switching function, there is more than one combination to produce each output voltage. Thus, redundancies of different switch configurations for generation of intermediate voltages are used to limit the deviation of capacitor voltages. The gate signals of the neutral-point clamped n-level converter can be calculated by inversing the modeling parts. Here, line-to-line voltage space vector modulation for a neutral-point clamped n-level converter is designed without using a Parks transform. Moreover, n × (n – 1) redundant vectors are used for DC bus voltage balancing. To highlight the performances of the developed modulation strategy, simulation results are given for five- and seven-level neutral-point clamped converters. Experimental results are given for a neutral-point clamped three-level converter.

Formalization and configuration methodology for high-radix combined switches

In large switch-based interconnection networks, increasing the switch radix results in a decrease in the total number of network components, and consequently the overall cost of the network can be significantly reduced. Moreover, high-radix switches are an attractive option to improve the network performance in terms of latency since hop count is also reduced. However, there are some difficulties related to integration scale to design such switches. In this paper we present and formalize an interesting alternative for building high-radix switches going beyond the integration scale bounds. The idea basically consists in combining several current smaller switches to obtain switches having greater number of ports. This strategy will remain valid as the scale of integration keeps evolving. Although simple, this strategy raises key design challenges in order to these high-radix switches achieve the best performance. The resultant internal structure of these switches becomes an important design decision, and an arbitrary selection may produce a significant performance degradation. For this reason, we also propose a general methodology to configure in an optimal way the internal switch structure and apply it to a particular case in order to show how it works. The resultant switch configurations are evaluated in order to show the real potential of our proposal.

Nanomechanical switches based on metal-insulator-metal capacitors from a standard complementary-metal-oxide semiconductor technology

We report experimental demonstrations of contact-mode nano-electromechanical switches obtained using a capacitor module based on metal-insulator-metal configuration of a standard commercial complementary metal oxide semiconductor technology. The developed 2 terminals Titanium Nitride switches operate at low voltages (∼10 V) thanks to its small gap (27 nm), showing an excellent ION/IOFF ratio (104) and abrupt behavior (5 mV/decade, one decade of current change is achieved with a 5 mV voltage variation). A switch configuration is also presented where using two electrodes three different contact mode states can be obtained, adding functionalities to mechanical switches configurations.

Clear evidence of mechanical deformation in RF-MEMS switches during prolonged actuation

Dielectric charging is normally considered one of the most important problems when dealing with RF-MEMS switch reliability, especially for applications which require long-term operation. Other important effects are therefore often neglected. In this paper we demonstrate that, for the case of long-term actuation in dielectric-less switches, the most important issue for switch reliability is not dielectric charging but viscoelastic deformation and creep of the mobile membrane. The measurements and the analysis are performed both for a cantilever and for a clamped–clamped switch configuration, evidencing that in the first case the mechanical deformations are more pronounced, and that they can justify almost completely the variation of actuation and release voltage experimentally measured. Mechanical deformation is also detected in a clamped–clamped switch, but it is less evident than that in the previous case. Nonetheless, even in this case they are responsible for most of the actuation and de-actuation voltage change experimentally detected.

The Well-Connected Processor Array

A new theoretical model for reconfigurable processor arrays is introduced. Most of the models considered in the literature are similar to the reconfigurable mesh (RMESH), in which each processing element (PE) is connected to its four neighbors by reconfigurable buses. In the new model, called the “well-connected processor array” (wecpar), every PE is connected to each neighbor by ${\mbi{k}} {\bf \geq 1}$ point-to-point lines, and it also controls the switching between those lines. ${\mbi{k}}$ is called the connectivity of the wecpar. Any line entering the PE can either be connected to the PE itself, or it can be connected by the PE to another line, thus enabling complex switching configurations. This model is suitable for arrays in which the computation and memory areas of a PE are very much larger than a switch area. The concept of a burden placed on a PE by the lines connected to or passing through it is introduced. This is used to derive a lower bound of ${\mbi{k}}=\Omegab({\mbi{d}}^{\bf 3/2}/{\mbi{e}})$ on the connectivity required by a wecpar to embed any graph of degree ${\bf \geq}{\mbi{d}}$ with expansion ${\mbi{e}}$ ; for ${\mbi{e}} {\bf = 1}$ , this result is sharp. Various other issues are examined: graph embeddings, algorithms, broadcasting, routing, and self-simulation. A novel transportation-type routing method utilizes the connectivity for efficient routing. A sample algorithmic result is that an ${\mbi{n}}$ -point FFT can be done in logarithmic time on a wecpar of ${\mbi{n}}$ PEs with a connectivity of $\sqrt{{\mbi{n}}/{\bf 2}}$ .

Theoretical investigation of a polymer Mach–Zehnder electro-optic switch using 2N + 1 serial-coupled microrings with ultralow-driving voltage

Universal structure and thorough analysis are proposed for a kind of (2N + 1)th order polymer microring resonator Mach–Zehnder interferometer (MRR-MZI) electro-optic (EO) switch. Formulas and expressions of output power, insertion loss and crosstalk are derived, and detailed design and optimization are carried out. Analytical results indicate that, besides the first-order MRR-MZI EO switch (N = 0), other devices for N ≥ 1 can all perform normal switching function, and 5 ≥ N ≥ 2 is preferred for dropping the crosstalk below −10 dB. For the four MRR EO switches (N = 2–5), their switching voltages are 0.99, 0.73, 0.57 and 0.47 V, respectively; their insertion losses are within the range of 1.15–2.26 dB at bar state, whereas those are within the range of 1.95–2.42 dB at cross state; their crosstalks are within the range of 11.04–17.82 dB at bar state, whereas those are within the range of 10.34–12.51 dB at cross state. Compared with the traditional MZI EO switch, the voltage–length product (0.21 V mm) of this switching element is decreased by ~111.7 times under the same waveguide parameters. Therefore, due to small footprint size and extremely low switching voltage, this switching configuration can be densely integrated onto optoelectronic chips.

Evaluating the Impact of Software-defined Networks’ Reactive Routing on BitTorrent Performance

Software-Defined Networks’ technologies introduce programmatic ways to reorganize the network logical topology. To achieve this, the switches in the network interact with a set of controllers, these controllers can dynamically update the switches configuration based in received events. A possible practical field of use of Software-Defined Networks’ is the one called Reactive Routing. On Reactive Routing the logical topology is continuously evolving based on traffic statistics as load or jitter which can be collected by the switches. BitTorrent is a well-known peer-to-peer protocol used on application layer to achieve fast propagation of content. In an effort to find the best set of connections that maximizes the global aggregation of throughput without knowledge from underlying topology, BitTorrent uses choking algorithms that continuously open and close connections to different peers. Software Defined Networks implementing Reactive Routing may be negatively affecting the performances of the system under specific conditions because of it lack of knowledge of BitTorrent strategies. Here, we review the concepts involved in Software-Defined Networks and BitTorrent protocol, we propose a classification of scenarios where these technologies may interact, we discuss hypotheses about possible problems arising from these interaction and we show our preliminary experimental results from study the phenomena.

Simple Switching Strategy for High-Torque Control Performance utilizing Neutral Point Clamped Multilevel Inverter

Three-level Neutral Point Clamped (NPC) inverter allows the configuration of switching devices to operate at high voltage and produce lower current/voltage harmonics. It is known that, DTC of induction machine which employs hysteresis controller has major drawbacks namely larger torque ripple and variable switching frequency. This paper aims to propose a suitable voltage vector selection to provide better torque regulation and lower switching frequency by employing DTC with 3-level NPC multilevel inverter. A simple switching strategy was formulated using 7-level torque hysteresis and 2-level flux hysteresis controllers to give more options in selecting an appropriate voltage vector, inherently, according the motor operation conditions. The improvements offered were verified through simulations. DOI: http://dx.doi.org/10.11591/ijpeds.v3i4.5248

Reconfiguration of distribution system through two minimum‐current neighbour‐chain updating methods

This study presents a new two-stage heuristic algorithm for loss-reduction reconfiguration of radial electrical distribution system. In the first stage, which is a close-all-switch technique and based on successively opening the minimum-current branches, the algorithm determines a feasible solution for the switch configuration. The second stage uses a neighbour-chain updating process (NCUP), which periodically updates each open switch of the configuration with its best neighbourhood switches. Depending on applicability of the circular mechanism on NCUP, two methods are utilised. The results of applying the proposed methods on five standard hypothetical or practical test networks demonstrate their excellent performance in obtaining best-known solutions in a systematic manner.

Behaviour Evaluation of GOOSE Message Traffic between Power Substations: A POTT Scheme Case Study

The aim of this paper is to evaluate the behaviour of GOOSE message traffic between two power substations using Ethernet technologies for POTT (permissive overreaching transfer trip) schemes. Moreover, a loss of messages between publisher and subscriber is closely monitored. Two main operation scenarios were defined and for each one of them some parameter variation took place, such as traffic intensity, as well as logical changes. Taking this into account, a practical laboratory was set up in order to carry out these experiments. This practical apparatus mainly consists of three digital relays, Ethernet switches, media converters, IBM personal computers, 20 km fibre optic cable, as well as support software. The results have been shown that the GOOSE messages can be applied for inter-substation communication, delivering a transfer time around 4.4 ms. Besides, traffic condition and switch configuration can heavily influence the time behaviour and loss of GOOSE messages used for POTT schemes in power systems.

Ag/GeSx/Pt-based complementary resistive switches for hybrid CMOS/nanoelectronic logic and memory architectures.

Complementary resistive switches based on two anti-serially connected Ag/GeSx/Pt devices were studied. The main focus was placed on the pulse mode properties as typically required in memory and logic applications. A self-designed measurement setup was applied to access each CRS part-cell individually. Our findings reveal the existence of two distinct read voltage regimes enabling both spike read as well as level read approaches. Furthermore, we experimentally verified the theoretically predicted kinetic properties in terms of pulse height vs. switching time relationship. The results obtained by this alternative approach allow a significant improvement of the basic understanding of the interplay between the two part-cells in a complementary resistive switch configuration. Furthermore, from these observations we can deduce a simplified write voltage scheme which is applicable for the considered type of memory cell.

Mobile Learning Application for Basic Router and Switch Configuration on Android Platform

This paper presents the design and development of Mobile Learning Application for Basic Router and Switch Configuration on Android Platform using Java Programming Language to help students in computer networking courses at the Department of Computer Technology and Networking, Faculty of Computer and Mathematical Sciences, University of Technology Mara, Malaysia. Our approach is to incorporate multimedia animations concept with command langguage to create the pervasive learning environment in presenting the Router and Switch Configuration systematically. With this mobile learning application, student could learn at his or her own pace, anywhere and anytime. This mobile learning application intends to complement the current traditional classroom and e-learning systems. Initial testing has shown that a well-presented multimedia animations capability that is delivered through a mobile phone has a great potential to promote and enhance learning process.

The Analysis of Switch Installing Optimization Based on FMEA Algorithm

In this paper, the distribution network structures divided as per the possible state configuration sequences based on different switch states (close/open) are analyzed with FMEA algorithm and calculated with regional equivalent improvement method. All switch configuration solutions will be assessed after the different regional economic advantages are fully considered and then the highest power availability solution on average is found. The case research shows that when the switch configuration comes to 111001, we get relatively balanced powersupply load of every branch and relatively high standard indexes.

The Analysis of Switch Installing Optimization Based on FMEA Algorithm

In this paper, the distribution network structures divided as per the possible state configuration sequences based on different switch states (close/open) are analyzed with FMEA algorithm and calculated with regional equivalent improvement method. All switch configuration solutions will be assessed after the different regional economic advantages are fully considered and then the highest power availability solution on average is found. The case research shows that when the switch configuration comes to 111001, we get relatively balanced powersupply load of every branch and relatively high standard indexes.

REAL TIME PERFORMANCE ANALYSIS OF BUCK DC-DC CONVERTER

Buck converter high side switching configuration can affect substantial reduction in power converter performances, allowing considerable higher power losses. This paper investigates a buck topology that achieves improved perfomance of direct current dc-dc buck converter by increasing duty cycle and by selecting low side switching configuration to reduce the power losses . The performance of buck converter for both high side switching configuration and low side switching configuration is analyzed. The design of buck converter circuit are investigated. The experimental results demonstrate the feasibility and high performance of the dc- dc buck converter. The analysis is verified experimentally using LVDAC - EMS.

High gain observer for a three‐cell chopper: Design and experimental results

SUMMARYAs capacitor voltages are necessary for the three‐cell DC–DC chopper control, the estimation of such voltages by an observer is attractive solution in terms of cost. However, due to the hybrid behavior of this structure, the capacitor voltages may be partially or even not observable for a given switching configuration. In other words, the observability matrix associated to the capacitor voltages never has a full rank. In order to make the observer conceivable, this paper proposes a new design by establishing sufficient conditions under which the capacitor voltages can be reconstructed within appropriate specific switching sequence and not necessarily instantly. An interconnected high gain observer is then designed for the considered structure. Furthermore, the analysis of convergence is given according to specific switching sequence, and the bounds of the observer tuning parameters are numerically verified. A significant load current benchmark including a three‐cell chopper is used as prototype to show the performance and the effectiveness of the proposed observer. Copyright © 2013 John Wiley & Sons, Ltd.

All-optical switching in Sagnac loop mirror containing an ytterbium-doped fiber and fiber Bragg grating

A configuration of all-optical switching based on a Signac loop mirror that incorporates an ytterbium-doped fiber and uniform fiber Bragg grating (FBG) is proposed in this paper. It is found that the transmission spectrum of this structure is the narrow splitting of the reflection spectrum of the FBG. The shift of this ultranarrow transmission spectrum is very sensitive to the intensity of the pump power. Thus, the threshold switching power can be greatly reduced by shifting such narrow transmission spectrum. Compared with the single FBG, the threshold switching power of this configuration is reduced by 4 orders of magnitude. In addition, the results indicate that this optical switching has a high extinction ratio of 20 dB and a ultrafast response time of 3 ns. The operation regime and switching performance under the cross-phase modulation cases are also investigated.

Obtaining the optimal configuration of high-radix Combined switches

High-radix switches reduce network cost and improve network performance, especially in large switch-based interconnection networks. However, there are some problems related to the integration scale to implement such switches in a single chip. An interesting alternative for building high-radix switches consists of combining several current smaller single-chip switches to obtain switches with a greater number of ports. A key design issue of this kind of high-radix switches is the internal switch configuration, specifically, the correspondence between the ports of these high-radix switches and the ports of their smaller internal single-chip switches. In this paper we use artificial intelligence and data mining techniques in order to obtain the optimal internal configuration of all the switches in the network of large supercomputers running parallel applications. Simulation results show that using the resultant switch configurations, it is possible to achieve similar performance as with single-chip switches with the same radix, which would be unfeasible with the current integration scale.

Optimization of Microring-Based Interconnection by Leveraging the Asymmetric Behaviors of Switching Elements

With the objectives of reducing power consumption, insertion loss, nonuniformity and crosstalk, optimal configurations for optical interconnection are derived, by leveraging the unequal characteristics at bar or cross state of microring switching elements. A novel and efficient heuristic is proposed for finding the optimum switching configuration. It is shown that the optimum average total insertion loss per path using 2 $\,\times\,$ 2 Basic Switching Element (2B-SE) achieves a 3.65-dB improvement for 128 $\,\times\,$ 128 switch size. The optimum average total insertion loss using 2B-SE in the worst-cast path is shown to be 7.2 dB less than the baseline values. Furthermore, for 128 $\,\times\,$ 128 switch size, the minimum improvement is 7.2 dB for the nonuniformity in the worst case, whereas the total crosstalk has a 2.43-dB improvement. The effect of non-uniform switch elements is also studied.