Switch Allocation Research Articles

Metaheuristic algorithms for capacitated controller placement in software defined networks considering failure resilience

SummarySoftware‐defined networking (SDN) has revolutionized network architectures by decoupling the control plane from the data plane. An intriguing challenge within this paradigm is the strategic placement of controllers and the allocation of switches to optimize network performance and resilience. In the event of a controller failure, the switches are disconnected from the controller until they are reassigned to other active controllers possessing sufficient spare capacity. The reassignment could lead to a significant rise in propagation latency. This correspondence presents a mathematical model for capacitated controller placement, strategically designed to anticipate failures and prevent a substantial increase in worst‐case latency and disconnections. The aim is to minimize the worst‐case latency between switches and their backup controllers and among the controllers. Four metaheuristic algorithms are proposed including, an enhanced genetic algorithm (CCPCFR‐EGA), particle swarm optimization (CCPCFR‐PSO), a hybrid particle swarm optimization and simulated annealing algorithm (CCPCFR‐HPSOSA), and a grey wolf optimization algorithm (CCPCFR‐GWO). These algorithms are compared with a simulated annealing method and an optimal method. Evaluation conducted on four network datasets demonstrates that the proposed metaheuristic methods are faster than the optimal method. The experimental outcome indicates that CCPCFR‐HPSOSA and CCPCFR‐GWO outperform the other methods, consistently providing near‐optimal solutions. However, CCPCFR‐GWO is preferred over CCPCFR‐HPSOSA due to its faster execution time. Specifically, CCPCFR‐GWO achieves an average speed‐up of 3.9 over the optimal for smaller networks and an average speed‐up of 31.78 for larger networks, while still producing near‐optimal solutions.

AS-Router: A novel allocation service for efficient Network-on-Chip

Assigning input ports to output ports and allowing flits to pass through the switch without colliding is accomplished by Switch Allocation (SA), a crucial pipeline stage in the Network-on-Chip (NoC) router. Earlier research improved the efficiency of matching to enhance SA processes. The studies in question, however, failed to account for the importance of information sharing between the various phases of the router’s pipeline. To improve NoC routers’ allocation, this article introduces the Allocation Service (AS) concept. By adding a new pipeline stage called Request Finalization (RF) before the SA stage, the AS can be optimized. The RF stage’s objective is to complete the uniform request and Endpoint Congestion Causing (EPC) requests for SA before sending them on their way. These results inform the proposal of a new design, the CUE-Router, to increase AS by the integration of an RF stage and inter-pipeline communication between routers. Two new types of router architecture form the basis for CUE-Router. The first thing we do in this work is introduce URR-Router, a router that only allocates EPC requests if there are no uniform requests in the SA stage, effectively giving uniform requests a priority. The second example is the EPR-Router, which alleviates endpoint congestion by favoring EPC requests over uniform ones. In this work, we take a fresh look at the SA process optimization that underpins the low-latency CUE-Router architecture by cycling through a series of prioritization changes between uniform requests and EPC requests. CUE-Router greatly improves SA efficiency and network performance by facilitating communication between the various stages of the pipeline. Based on the results of the analysis, our approach has the potential to significantly enhance performance with minimal additional effort.

Switch Allocation Problem in Power Distribution Systems with Distributed Generation

Switch Allocation Problem in Power Distribution Systems with Distributed Generation

Distribution systems cost reduction based on switches upgrades: A stochastic approach

Power Distribution Systems are considered critical infrastructures, and their continuity to deliver and maintain electricity to the final customer is of extreme importance. The Optimal Switch Allocation address this topic by changing the network configuration to improve reliability, while minimizing power loss and cost. On previous researches economic constraints and dynamic failure models were considered, but neither the uncertainty in the environmental parameters nor stochastic models are applied. Additionally, the possibility to upgrade existing switches are often not considered. This work applies a Genetic Algorithm, coupled with Monte Carlo Simulation, as well as a Bayesian Inference Model, to address the probability of upgrading existing switches in a power distribution system. Economical constraints, fragility curves, variable load demand and weather scenarios are simulated. The Bayesian inference allows the model to be used as a support decision tool, when dealing with the possibility of upgrading switches in the network, especially in face of uncertainties in the distribution system. Results show that the upgrade of existing switches can achieve total cost reduction, but the uncertainties presented in the model can change the probability of upgrading an individual switch, thus sustaining the importance of the proposed approach. • A stochastic approach to deal with the upgrade of switches in a distribution system. • Monte Carlo method and genetic algorithm are used to simulate failure scenarios. • A Bayesian hierarchical approach fit the data into a final statistical model. • The final solution is the posterior probability of each switch upgrade. • The method quantifies the importance of each switch, enabling decision support.

Interruption flows for reliability evaluation of power distribution networks

Energy networks should strive for reliability. How can it be assessed, measured, and improved? What are the best trade-offs between investments and their worth? The flow-based framework for the reliability assessment of energy networks proposed in this paper addresses these questions with a focus on power distribution networks. The framework introduces the concept of iflows, or interruption flows, which translate the analytical reliability evaluation into solving a series of node balance equations computable in linear time. The iflows permeate the network, providing relevant information to support linear formulations of reliability optimization problems. Numerical examples showcase the evaluation process obtained through iflows in illustrative distribution networks with distributed generation. A new visual representation of the reliability state, called iflow diagram, provides insights into the most vulnerable regions of the network. The methodology was validated by a practical application of the iflows on the optimal allocation of switches in power distribution systems. Computational experiments were conducted using a benchmark of distribution networks, having up to 881 nodes. The results confirm the effectiveness of the approach in terms of providing high-quality information and optimal trade-offs to aid reliability decisions for energy networks.

On the MILP Modeling of Remote-Controlled Switch and Field Circuit Breaker Malfunctions in Distribution System Switch Placement

Installing sectionalizing switches and field circuit breakers (FCBs) is vital for the fast restoration of customer electricity supply in distribution systems. However, the high capital costs of these protection devices, especially remote-controlled switches (RCSs) and FCBs, necessitate finding a trade-off between their costs and financial benefits. In this study, we propose a mixed-integer linear programming (MILP) model for optimizing switch planning in distribution systems. The proposed model determines the optimal allocation of manual switches, RCSs, and FCBs to minimize the costs of switches and the reliability-oriented expenses. While the former includes the costs of installing and operating the switches, the latter consists of the distribution company’s lost revenue due to the undelivered energy and the regulatory incentives (or penalties) associated with service reliability indices. Two penalty-reward mechanisms are used to account for the financial benefits of increasing the service reliability through reducing the duration and frequency of interruptions. Proposing a novel reliability assessment model, we consider the possibility of malfunctions in both RCSs and FCBs in a highly efficient manner, which is a major contribution of this work. The proposed MILP model is applied to three test networks to validate its applicability and efficacy. The results show the importance of considering the possibility of switch malfunctions in distribution networks.

Optimization of Switch Allocation Problems in Power Distribution Networks

This paper presents the implementation of the mono-objective Switch Allocation Problem (SAP) optimization model for electric power distribution networks, considering the equivalent interruption duration per consumer unit EIDCU and non-distributed energy END reliability indexes. We use the current summation algorithm to solve the power flow, and we employ an intelligent bee colony algorithm to solve the model. Two network topologies, one with 43 and another with 136 bars, adapted from the literature, are used to illustrate the solution. Results show a significant reduction in the financial cost of planning a power distribution network.

Continuous versus Bolus Gastric Tube Feeding in Very Low Birth Weight Infants Supported with Noninvasive Respiratory Support: A Randomized, Pilot Study.

This study aimed to compare time to full feeding (TFF) between continuous gastric feeding (CGF) and bolus feeding (BF) in very low birth weight (VLBW) infants supported with noninvasive ventilation (NIV) and to evaluate feasibility and identify methodological pitfalls for future large-scale studies. This study is a randomized controlled, prospective, pilot study. VLBW premature infants, supported with NIV, were randomized while still on trophic feeding <20 mL/kg/day to receive feeding over 2 hours of CGF or over 15- to 30-minute BF. The primary outcome was TFF. Analysis was done by intention to treat. Overall, 32 infants were included in this analysis, 17 in the CGF group and 15 in the BF group. Infants in the CGF group were significantly younger than the BF group (mean ± standard deviation [SD] gestational age [GA] 26.9 ± 1.2 vs. 28.9 ± 1.5 weeks, respectively). TFF was comparable with median (interquartile range [IQR]) for the two groups, 10.0 (10.0, 19.0) days in the BF group versus 12.0 (9.0, 13.0) days in the CGF group (p = 0.59). Feeding length was not found to significantly affect TFF in multivariate analysis correcting for GA. Groups were comparable in weight gain, gastrointestinal complications, length of NIV, bronchopulmonary dysplasia incidence, and age at discharge. Most infants from both groups (60% of BF and 70% of CGF) required changes in feeding length. In this pilot study, among VLBW infants supported with NIV, TFF was comparable between the BF and CGF groups. These results should be interpreted with caution due to the small sample size and despite the multivariate analysis correcting for the different GA. Interestingly, most infants required changes in feeding length regardless of their allocation. This feasibility study emphasizes the need for careful attention to randomization and strict feeding protocols including criteria for switching allocation in future large-scale studies aimed at determining the preferred feeding length during NIV in VLBW infants. · Among infants supported with NIV, length of feeding affects gastric venting.. · BF might increase gastrointestinal reflux, while continuous feeding hinders gastric decompression.. · Among infants supported by NIV, feeding tolerance was comparable between bolus and continuous groups..

MUA-Router: Maximizing the Utility-of-Allocation for On-chip Pipelining Routers

As an important pipeline stage in the router of Network-on-Chips, switch allocation assigns output ports to input ports and allows flits to transit through the switch without conflicts. Previous work designed efficient switch allocation strategies by maximizing the matching efficiency in time series. However, those works neglected the interaction between different router pipeline stages. In this article, we propose the concept of Utility-of-Allocation (UoA) to indicate the quality of allocation to be practically used in on-chip routers. We demonstrate that router pipelines can interact with each other, and the UoA can be maximized if the interaction between router pipelines is taken into consideration. Based on these observations, a novel class of routers, MUA-Router, is proposed to maximize the UoA through the collaborative design (co-design) between router pipelines. MUA-Router achieves this goal in two ways and accordingly implements two novel instance router architectures. In the first, MUA-Router improves the UoA by mitigating the impact of endpoint congestion in the switch allocation, and thus Eca-Router is proposed. Eca-Router achieves an endpoint-congestion-aware switch allocation through the co-design between routing computation and switch allocation. Based on Eca-Router, CoD-Router is proposed to feed back switch allocation information to routing computation stage to provide switch allocator with more conflict-free requests. Through the co-design between pipelines, MUA-Router significantly improves the efficiency of switch allocation and the performance of the entire network. Evaluation results show that our design can achieve significant performance improvement with moderate overheads.

RETRACTED: Design and implementation of network‐on‐chip router using multi‐priority based iterative round‐robin matching with slip

AbstractNowadays, network‐on‐chip (NoC) routers become important in several applications including mobile technology and digital communication. Multiple cores/processors are typically coupled using NoC routers, which considerably improve integrated circuit performance in terms of power, latency, throughput, and area. So, a novel 4 × 4 topology‐based NoC router using multi‐priority based iterative round‐robin matching with slip (MPiSLIP) routing algorithm is implemented in this work. The proposed work contains different operational blocks classification such as route computation using static straight allocator, route controlling using MPiSLIP arbiter, a crossbar switch, combined parallel virtual channel and switch allocation unit, look ahead bypass route computation (LBRC), and input‐output ports. The MPiSLIP routing mechanism also determines the priorities necessary for route development. Finally, by bypassing the switches and fulfilling all of the priories in a look‐ahead manner, LBRC is employed to establish the effective path between input ports and output ports. The simulation results show that the proposed MPiSLIP‐based NoC routing method resulted in a reduced area, power, and latency as compared to the open‐source NoCs, multi‐processor NoCs, multi‐core NoCs, and conventional routing algorithms.

An Effective Approach for Controller Placement in Software-Defined Internet-of-Things (SD-IoT).

The Software-Defined Networking (SDN) paradigm has transferred network intelligence from network devices to a centralized controller. Controllers are distributed in a network to eliminate a single point of failure (SPOF) and improve reliability and balance load. In Software-Defined Internet of Things (SD-IoT), sensors exchange data with a controller on a regular basis. If the controllers are not appropriately located in SD-IoT, the E2E latency between the switches, to which the sensors are connected, and the controller increases. However, examining the placement of controllers in relation to the whole network is not an efficient technique since applying the objective function to the entire network is a difficult operation. As a result, segmenting the network into clusters improves the efficiency with which switches are assigned to the controller. As a result, in this research, we offer an effective clustering strategy for controller placement in SDN that leverages the Analytical Network Process (ANP), a multi-criteria decision-making (MCDM) scheme. The simulation results demonstrated on real Internet topologies suggest that our proposed method outperforms the standard k-means approach in terms of E2E delay, controller-to-controller (C2C) delay, the fair allocation of switches in the network, and the communication overhead.

Implementation of Dynamic and Efficient Virtual Channel Router for Network on Chip with Virtual Channel Arbitration Reduction and Parallel Switch Allocation Unit

— Network on chip (NoC) is a new method of interconnecting modules in system on chip (SoC). Now a day, it is believed that this new communication subsystem will replace the bus-based architecture and will become dominant in SoC design technology. The performance of NoC mainly depends on the router so it is considered as the crucial part in the NoC design. This paper describes the different factors which affect the NoC performance and provides solution to solve these problems. The proposed router has three architectural modifications which makes it dynamic and efficient as compare to generic virtual channel router. This paper introduced the dynamic buffer allocation scheme in which virtual channels and buffer slots are selected and allocated dynamically depending on the network traffic conditions in real time which in turn increases the throughput. In this paper, we have focused on optimizing the virtual channel arbitration (VA) unit design and switch allocation (SA) unit design as well as focusing the maximum utilization of buffer so that it will result in minimizing the latency, area and power. The source code of the router is written in VHDL hardware description language and the simulation and synthesizing the router is done in Xilinx ISE Design Suite 13.1. The parameters like area, frequency, delay, power, latency and throughput are calculated. The results of this modified virtual channel router are compared with the generic virtual channel router. Keywords—Intellectual Property (IP), Network on Chip (NoC), Network Interface (NI), Switch allocation (SA), System-on-Chip (SoC), Virtual channel (VC), Virtual channel arbitration (VA)

A Variable Neighbourhood Search Approach to Optimal Switch Allocation Problem

A Variable Neighbourhood Search Approach to Optimal Switch Allocation Problem

SB-Router: A Swapped Buffer Activated Low Latency Network-on-Chip Router

Switch Allocation (SA) holds a critical stage in Network-on-Chip (NoC) routers, its performance gets affected adversely due to Head-of-Line (HoL) blocking. In traditionally used Input-Queued Routers (IQR), packets are arranged in a particular order in each Virtual Channel (VC). This implementation is vulnerable to HoL blocking, as the switch allocator can allocate only those packets which are available at the head in a VC. In this paper, Swapped Buffer (SB) Router architecture is proposed to schedule packets in input buffers by using SB registers. The VCs are designed as SBs, this allows the packets stored in SB registers along with the head packet of VC to participate in SA. The concept of the SB register minimizes the conflicts in SA and thus reduces HoL blocking, therefore improves the performance of NoC. This paper proposes a priority mechanism to prioritize the non-head packets as compared to head packets in case of conflict between them. Two methods have been proposed in this paper, to enhance the performance of the NoC router. First, a VC allocation technique is proposed to optimize the order of packets in the input buffer. Next, SB-Router is combined with the Fill VC allocation technique to further enhance the performance of NoC routers. The performance of the proposed router is evaluated and the experimental results indicate that our design achieves latency improvement of 68.75% over (Time-Series) TS-Router for uniform traffic at the injection rate of 0.42 flits/cycle for a 64 node mesh network with moderate power consumption and area usage. The performance improvement in packet latency for traces from Princeton Application Repository for Shared-Memory Computers (PARSEC) has also been evaluated. With the achieved reduction in latency, the proposed method has the potential to serve high-speed operations while mapping different applications on multiple core architectures.

Reliability Analysis and Improvement of Debre Berhan Power Distribution Network by Using Fuzzy Logic Optimization Technique

This paper presents determination and allocation optimal number of sectionalizer switches using fuzzy based approach to improve the reliability of Berhan power distribution network. My intention to present in this study on the reliability assessment and method of improving reliability is that Debre Berhan power distribution network has frequent instructions. To improve customer reliability of power distribution system different methods can be used. Thus to complete this study MATLAB Simulink models of distribution network initial and optimal number of sectionalizer switch allocation are developed. Sheno 15kV feeder of the distribution network is selected for simulation studies to test the efficiency of the proposed approach. Simulation studies using ETAP software are carried out reliability indies of distribution network with and without optimal number of switch allocation. The simulation results show optimal allocation of sectionalizer switches improve the reliabity indices such as SAIFI, SAIDI and expected energy not supplied (EENS) and evaluates the reliability of Debre Berhan power distribution network using analytical techniques, software simulation and level of optimization achievable through the application optimal placement of switches. At the result of optimal placement of sectionalizers switches for sheno 15kV feeder SAIFI is improved by 12.76% and SAIDI are 41.61%. From the test result the proposed technique presents better interruption cost in comparison that of existing system 64,806.06$/yr. to 57,346.57$/yr. (which is 11.5% reduction) along with improvement in reliability indices and expected energy not supplied (EENS) was improved from 17828.014MWh/yr. to1533.75MWh/yr. (91.04%).

Savior: A Reliable Fault Resilient Router Architecture for Network-on-Chip

The router plays an important role in communication among different processing cores in on-chip networks. Technology scaling on one hand has enabled the designers to integrate multiple processing components on a single chip; on the other hand, it becomes the reason for faults. A generic router consists of the buffers and pipeline stages. A single fault may result in an undesirable situation of degraded performance or a whole chip may stop working. Therefore, it is necessary to provide permanent fault tolerance to all the components of the router. In this paper, we propose a mechanism that can tolerate permanent faults that occur in the router. We exploit the fault-tolerant techniques of resource sharing and paring between components for the input port unit and routing computation (RC) unit, the resource borrowing for virtual channel allocator (VA) and multiple paths for switch allocator (SA) and crossbar (XB). The experimental results and analysis show that the proposed mechanism enhances the reliability of the router architecture towards permanent faults at the cost of 29% area overhead. The proposed router architecture achieves the highest Silicon Protection Factor (SPF) metric, which is 24.8 as compared to the state-of-the-art fault-tolerant architectures. It incurs an increase in latency for SPLASH2 and PARSEC benchmark traffics, which is minimal as compared to the baseline router.

Improvement of Reliability Indices and Costs in Distribution Systems Considering Multiple Scenarios Through Switch Reallocation

This paper presents a method for improving indices and costs associated with reliability in radial distribution systems through switch placement using genetic algorithms. On this paper, the switch allocation problem will be solved with a method that allows novelties that can improve the quality of the solutions obtained. First, the possibility of switch allocation on both sides of each section of a feeder is proposed. Second, a method to quantify the non-supplied energy in terms of dollars per kWh of interruption is expanded, allowing a versatile way to simulate cases in which individual customers have different economic impacts when in situation of interrupted power delivery. The proposed algorithm is also versatile when additional restrictions are applied, such as fixing the number of switches or imposing SAIDI limits. Optimal switch locations are defined to improve restoration and reduce costs associated with reliability. Simulations in test and real feeders are performed, and the presented results show significant improvements.

Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things.

Network-on-chip (NoC) architectures have become a popular communication platform for heterogeneous computing systems owing to their scalability and high performance. Aggressive technology scaling makes these architectures prone to both permanent and transient faults. This study focuses on the tolerance of a NoC router to permanent faults. A permanent fault in a NoC router severely impacts the performance of the entire network. Thus, it is necessary to incorporate component-level protection techniques in a router. In the proposed scheme, the input port utilizes a bypass path, virtual channel (VC) queuing, and VC closing strategies. Moreover, the routing computation stage utilizes spatial redundancy and double routing strategies, and the VC allocation stage utilizes spatial redundancy. The switch allocation stage utilizes run-time arbiter selection. The crossbar stage utilizes a triple bypass bus. The proposed router is highly fault-tolerant compared with the existing state-of-the-art fault-tolerant routers. The reliability of the proposed router is 7.98 times higher than that of the unprotected baseline router in terms of the mean-time-to-failure metric. The silicon protection factor metric is used to calculate the protection ability of the proposed router. Consequently, it is confirmed that the proposed router has a greater protection ability than the conventional fault-tolerant routers.

Self‐healing enhancement through co‐deployment of automatic switches and electric vehicle PLs in an electricity distribution network

Accomplishing highly reliable distribution grids is more and more important to today's modern society. Along the same line, self-healing is one of the most distinguishing features of the smart grid that could improve the reliability of the system up to a logical extent. In this study, the reliability of the electrical distribution grid has been improved by optimal allocation of automatic switches and parking lots (PLs). Thus, the optimal places of switches and PLs are determined with the purposes of minimising a combined effect of the customer-based (system average interruption duration index) and cost-based [total reliability cost (TRC)] reliability indices. The TRC includes customer interruption costs, PLs and automatic switches investment costs, and the total cost of PLs incorporation in the service restoration process. The proposed approach is implemented in three different planning scenarios: switch placement, PL placement, and joint switch and PL placement. The particle swarm optimisation method is employed to solve optimisation problems. Finally, a standard reliability test system bus number four of the Roy Billinton test system (RBTS 4) is used to demonstrate the efficacy of the proposed method.

NoCGuard: A Reliable Network-on-Chip Router Architecture

Aggressive scaling in deep nanometer technology enables chip multiprocessor design facilitated by the communication-centric architecture provided by Network-on-Chip (NoC). At the same time, it brings considerable challenges in reliability because a fault in the network architecture severely impacts the performance of a system. To deal with these reliability challenges, this research proposed NoCGuard, a reconfigurable architecture designed to tolerate multiple permanent faults in each pipeline stage of the generic router. NoCGuard router architecture uses four highly reliable and low-cost fault-tolerant strategies. We exploited resource borrowing and double routing strategy for the routing computation stage, default winner strategy for the virtual channel allocation stage, runtime arbiter selection and default winner strategy for the switch allocation stage and multiple secondary bypass paths strategy for the crossbar stage. Unlike existing reliable router architectures, our architecture features less redundancy, more fault tolerance, and high reliability. Reliability comparison using Mean Time to Failure (MTTF) metric shows 5.53-time improvement in a lifetime and using Silicon Protection Factor (SPF), 22-time improvement, which is better than state-of-the-art reliable router architectures. Synthesis results using 15 nm and 45 nm technology library show that additional circuitry incurs an area overhead of 28.7% and 28% respectively. Latency analysis using synthetic, PARSEC and SPLASH-2 traffic shows minor increase in performance by 3.41%, 12% and 15% respectively while providing high reliability.