Abstract
Network-on-chip (NoC) architectures have become a popular communication platform for heterogeneous computing systems owing to their scalability and high performance. Aggressive technology scaling makes these architectures prone to both permanent and transient faults. This study focuses on the tolerance of a NoC router to permanent faults. A permanent fault in a NoC router severely impacts the performance of the entire network. Thus, it is necessary to incorporate component-level protection techniques in a router. In the proposed scheme, the input port utilizes a bypass path, virtual channel (VC) queuing, and VC closing strategies. Moreover, the routing computation stage utilizes spatial redundancy and double routing strategies, and the VC allocation stage utilizes spatial redundancy. The switch allocation stage utilizes run-time arbiter selection. The crossbar stage utilizes a triple bypass bus. The proposed router is highly fault-tolerant compared with the existing state-of-the-art fault-tolerant routers. The reliability of the proposed router is 7.98 times higher than that of the unprotected baseline router in terms of the mean-time-to-failure metric. The silicon protection factor metric is used to calculate the protection ability of the proposed router. Consequently, it is confirmed that the proposed router has a greater protection ability than the conventional fault-tolerant routers.
Highlights
Applications that improve the lifestyles of users such as the Internet of things (IoT), cloud computing, and cognitive computing have attracted considerable attention in recent years [1,2].These applications and systems generate enormous amounts of data continuously [3]
This paper presents a fault-tolerant NoC router architecture that protects all the components of the router against permanent faults
NoC architectures are increasingly adopted in exascale heterogeneous computing systems owing to their scalability and performance
Summary
Applications that improve the lifestyles of users such as the Internet of things (IoT), cloud computing, and cognitive computing have attracted considerable attention in recent years [1,2]. Sensors 2020, 20, 5355 contribute to the design and development of ICPS These heterogeneous cores require scalable and high-performance communication infrastructure to exchange data. This paper presents a fault-tolerant NoC router architecture that protects all the components of the router against permanent faults. It tolerates multiple faults in the input port, route computation (RC), virtual channel allocation (VA), switch allocation (SA), and crossbar (XBAR) units. The XBAR stage utilizes a triple bypass bus strategy to bypass a faulty XBAR Owing to these features, the proposed router has a low area overhead and tolerates a high number of faults compared with the state-of-the-art fault-tolerant router. This study compares the latency, hardware consumption, and reliability of the proposed architecture with those of the state-of-the-art fault-tolerant router architectures
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