Abstract
Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing modules. However, the aggressive scaling of transistors makes NoC more vulnerable to both permanent and transient faults. Permanent faults persistently affect the circuit functionality from the time of their occurrence. The router represents the heart of the NoC. Thus, this research focuses on tolerating permanent faults in the router’s input buffer component, particularly the virtual channel state fields. These fields track packets from the moment they enter the input component until they leave to the next router. The hardware redundancy approach is used to tolerate the faults in these fields due to their crucial role in managing the router operation. A built-in self-test logic is integrated into the input port to periodically detect permanent faults without interrupting router operation. These approaches make the NoC router more reliable than the unprotected NoC router with a maximum of 17% and 16% area and power overheads, respectively. In addition, the hardware redundancy approach preserves the network performance in the presence of a single fault by avoiding the virtual channel closure.
Highlights
The advancements in the semiconductor industry towards deep-sub micrometer technologies were motivated by Moore’s law in the last decades, allowing the integration of billions of transistors on a single chip [1,2]
Network on chip (NoC) interconnection architecture appeared as an alternative on-chip interconnection in MPSoCs due to its high performance, reusability, scalability, and fault tolerance characteristics [1,4,5]
We review earlier works on fault-tolerant network on chip (NoC) router architectures that focus on tolerating permanent faults in the NoC router pipeline
Summary
The advancements in the semiconductor industry towards deep-sub micrometer technologies were motivated by Moore’s law in the last decades, allowing the integration of billions of transistors on a single chip [1,2] These chips embed hundreds of memory modules and functional intellectual property (IP) blocks forming multi/many-processor systems-on-chip (MPSoCs) [2,3]. Wormhole switching divides the packet into smaller fixed size parts called flits (flow control information units) and traverses them. The proposed scheme tolerates permanent (hard) faults in very important fields of the input. 72 buffer (port) component called the virtual channel state fields, which they track the flits the moment.
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