SVPWM Strategy Research Articles

A Four-level Inverter Scheme with Reduced Common Mode Voltage for an Induction Motor Drive

A four-level inverter configuration for an induction motor is proposed in this paper. The drive used for this scheme is an open-end winding induction motor which can be obtained by separating the neutral connections of any general three-phase induction motor. The proposed scheme uses two three-level inverters, with asymmetric DC link voltage, feeding the induction machine from both sides and can generate voltage space vector locations similar to a conventional seven-level inverter. The four-level scheme is based on the use of only those space vector combinations of the seven-level inverter, which generate zero common mode voltage in the machine phase voltages. The proposed four-level inverter scheme requires only two isolated DC links as compared to the conventional diode-clamped four-level inverter scheme, which needs three isolated power supplies. The common mode voltage, in the pole voltages of the proposed four-level inverter, is significantly lower than that of the conventional four-level inverter while the machine phase voltages have zero common mode content. The proposed power circuit bus structure is simple to fabricate when compared to the conventional four-level inverter. A SVPWM scheme is presented, which generates the inverter gate switching signals from sampled amplitudes of reference phase voltages. The proposed four-level inverter scheme is implemented of a 1.5 kW open-end winding induction motor and the experimental results are presented.

Current measurements in digitally controlled AC drives

In this article, the current-sampling error has been investigated in the field-oriented control of an AC machine by a PWM inverter. The expression of the harmonic current due to a low-pass filter has been studied analytically from the reference voltage vector in the SVPWM strategy. The fundamental components of the current-sampling error causes improper torque regulation while the high-frequency ripple of the error introduces permissible gain of the current regulators with a resultant impairment in dynamic behavior and limited stability range of the control systems. It has been proposed that the magnitude and phase error from the filter can be avoided with delayed sampling. The effectiveness of the delayed sampling was verified through simulations and experimental results including steady state and dynamic responses.