Surrounding-Gate Metal Oxide Semiconductor Research Articles

Quantum Modelling of Nanoscale Silicon Gate-All-Around Field Effect Transistor

The paper introduces an analytical model for gate all around (GAA) or Surrounding Gate Metal Oxide Semiconductor Field Effect Transistor (SG-MOSFET) inclusive of quantum mechanical effects. The classical oxide capacitance is replaced by the capacitance incorporating quantum effects by including the centroid parameter. The quantum variant of inversion charge distribution function, inversion layer capacitance, drain current, and transconductance expressions are modeled by employing this model. The established analytical model results agree with the simulated results, verifying these models' validity and providing theoretical supports for designing and applying these novel devices.

Effect of Gate Engineering and Channel Length Variation in Surrounding Gate MOSFETs

In this paper, the digital and analog performance for Double Material Gate Surrounding Gate Metal Oxide Semiconductor Field Effect Transistor (DM SG MOSFET) has been analyzed. A detailed study of DM SG MOSFET is performed for different channel length ratio's. The comparison analysis on surface potential, electric field, transfer characteristics, output characteristics, transconductance and output conductance is carried with respect to the silicon dioxide and hafnium dioxide based device. It has been found from the simulation results that HfO2 dielectric used DM SG TFET provides better performance than SiO2 dielectric used DM SG TFET. Also it has been observed from the presented results that the transconductance is 45.32 at 1:3 channel length ratio for DG SG MOSFET.

Design and analysis of high sensitivity photosensor using Cylindrical Surrounding Gate MOSFET for low power applications

In this paper, a high sensitivity photosensor is proposed that utilizes the Zinc Oxide (metallic ZnO) which act as a transparent optical window over channel. High sensitivity is achieved by using Cylindrical Surrounding Gate Metal Oxide Semiconductor Field Effect Transistor (CSG MOSFET). On being exposed to light there is substantial increase in conductance and thereby change in the subthreshold current under exposure is utilized as a sensitivity parameter. Most of the Conventional FET based photosensors that are available utilizes threshold voltage as the parameter for sensitivity comparison but in this proposed sensor, under illumination change in the conductance resulting in variation of the subthreshold current is considered to be the sensitivity parameter. Performance comparison with Double Gate Metal Oxide Semiconductor Field Effect Transistor (DG MOSFET) in terms of sensitivity, threshold voltage and Ion/Ioff ratio is also done and observed results shows that CSG MOSFET is an ideal candidate for being used as a high sensitivity photosensor because in CSG MOSFET due to effective control of gate over channel low dark current, high sensitivity, low threshold voltage and high Ion/Ioff ratio can be achieved. Further impact of channel radius on responsivity (Re), quantum efficiency (Qe) and Ion/Ioff ratio is also studied for the proposed device.

Analytical Model for Direct Tunneling Gate Current in Long-Channel Undoped Cylindrical Surrounding Gate Metal–Oxide–Semiconductor Field Effect Transistors

In this study, an analytical direct tunneling gate current model for long-channel undoped cylindrical surrounding gate (CSG) MOSFETs is developed. On the basis of an analytical model, the direct tunneling gate current in CSG MOSFETs is investigated. It is found that direct tunneling gate current is a strong function of gate oxide thickness, but less affected by the change in channel radius. It is also revealed that considering the influence of the source and drain, as the length of the underlap region decreases to zero, the direct tunneling gate current drastically increases. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.

Implicit Continuous Current–Voltage Model for Surrounding-Gate Metal–Oxide–Semiconductor Field-Effect Transistors Including Interface Traps

An analytic and continuous direct-current model for cylindrical doped surrounding-gate metal-oxide-semiconductor field-effect transistors (SGMOSFETs) including interface-trap charges is presented. Based on the SGMOSFET model, which is valid from undoped to heavily doped channels, a general model for long-channel SGMOSFETs including interface-trap charges is derived. A comparison between the numerical simulations and analytic calculations showed that the proposed model is valid for all operating regions of SGMOSFETs including different interface-trap charges with several dimensions and doping densities.

Analytical Model for Subthreshold Swing and Threshold Voltage of Surrounding Gate Metal–Oxide–Semiconductor Field-Effect Transistors

Analytical Model for Subthreshold Swing and Threshold Voltage of Surrounding Gate Metal–Oxide–Semiconductor Field-Effect Transistors

Analytical Model for Subthreshold Swing and Threshold Voltage of Surrounding Gate Metal–Oxide–Semiconductor Field-Effect Transistors

We investigate analytically the metal–oxide–semiconductor field-effect transistor (MOSFET) with a surrounding gate (SG). We develop and present an analytical model for subthreshold swing and threshold voltage. Poisson's equation is solved analytically. The analytical expressions for electrical potential, drain current in the subthreshold region, subthreshold swing, and threshold voltage are obtained. The analytical results are compared with simulated results, and the two agree very well. The subthreshold swing of an SG MOSFET can be improved either by reducing the silicon body radius or by reducing the oxide thickness. The threshold voltage decreases with reductions in the channel length, the silicon body radius, or the oxide thickness. Based on the threshold voltage model, drain induced barrier lowering (DIBL) effect is explored, and we find that DIBL effect is more severe for a device with a larger silicon body radius, and/or with a shorter channel length.

Analytical Threshold Model for Nanoscale Cylindrical Surrounding-Gate Metal–Oxide–Semiconductor Field Effect Transistor with High-κ Gate Dielectric and Tri-Material Gate Stack

A novel cylindrical surrounding-gate metal–oxide–semiconductor field effect transistor with high-κ gate dielectric and tri-material gate stack (TMGCSG MOSFET) is presented. The performance of the new structure is studied by developing physics-based analytical models for surface potential, electric field, and threshold voltage. It is found that TMGCSG MOSFET can effectively suppress short-channel effects and hot-carrier effects, and simultaneously improve carrier transport efficiency. It is also revealed that threshold voltage roll-off for TMGCSG MOSFET can be significantly reduced by adopting both a small effective stack-gate oxide thickness and a small radius silicon channel. The accuracy of the analytical models is verified by its good agreement with the three-dimensional numerical device simulator DESSIS.

Analytic Oxide Capacitance Model of Double- and Surrounding-Gate Metal–Oxide–Semiconductor Field-Effect Transistors in Linear Region by Considering Inversion-Layer Capacitance

Inversion charge (Qi) and oxide capacitance (Cox') of undoped (or lightly doped) or doped double-gate (DG) and surrounding-gate (SG) metal–oxide–semiconductor field-effect transistors (MOSFETs) with long channel were analytically modeled by considering inversion-layer capacitance (Ci) in linear region. The Qi model of DG and SG MOSFETs was derived with a closed-form as a function of gate bias (VGS), threshold voltage (Vth), and body structure factor (n) using one-dimensional (1D) Poisson's equation considering the mobile carrier. The n which reflects silicon body structure effect is 1 for DG MOSFETs and less than 1 for SG MOSFETs irrespective of channel doping (Nb). From the derived Qi model considering the Ci effect, the Cox' was modeled and applied to the ID–VGS model of undoped or doped DG and SG MOSFETs in linear region. The compact current model using our proposed Cox' predicted more accurately the on-current behavior than that with the oxide capacitance (Cox) in linear region.

Current Model of Fully Depleted Nanoscale Surrounding-Gate Metal–Oxide–Semiconductor Field-Effect Transistors with Doped Channel in All Operation Regions

The diffusion current of fully depleted (FD) nanoscale surrounding-gate (SG) metal–oxide–semiconductor field effect transistors (MOSFETs) with a doped channel was physically modeled with a simple closed form based on the surface potential. The potential distribution [\\varPhix(z)] of doped SG MOSFETs was derived using Young's simple approximation from a two-dimensional (2D) Poisson's equation. In the diffusion current model, to consider the dependence on gate bias (VGS) and drain bias (VDS), parameters (DG and DD) were introduced. In the saturation region, the drift current modeling of doped FD SG MOSFETs was easily performed from the derived current model in the linear region. The current of the devices in the transition region was also modeled with the simple closed form using the diffusion and drift current model. Our simple compact model accurately predicted the current behaviors of the devices with a channel length up to 20 nm and shown good agreement with three-dimensional (3D) simulation.

Improved Explicit Current–Voltage Model for Long-Channel Undoped Surrounding-Gate Metal Oxide Semiconductor Field Effect Transistor

The surrounding-gate metal oxide semiconductor field effect transistor (MOSFET) provides the best device structure for the control of the short channel effect. In this paper, we present an improved explicit current–voltage (I–V) model for a long-channel undoped surrounding-gate MOSFET. The derivation of this new model considers variations in silicon film radius and gate oxide thickness. For important cases of large silicon film radius and small gate oxide thickness, the new model shows a better agreement with a numerical solution than the previous explicit model. The accuracy of the new model is verified by comparison with numerical simulations.

Analytical Modeling and Simulation of Dual-Material Surrounding-Gate Metal–Oxide–Semiconductor Field Effect Transistors with Single-Halo Doping

We present a modified surrounding-gate metal–oxide–semiconductor field effect transistor (MOSFET), in which the gate consists of two metals with different work functions, and single-halo doping is added to the channel near the source end. The performance of the modified structure was studied by developing physics-based analytical models for the surface potential, electric field, and threshold voltage. It is shown that the novel MOSFET could significantly reduce threshold voltage roll-off and drain-induced barrier lowering, and simultaneously improve carrier transport efficiency by carefully configuring the halo doping and work functions of the dual-material gate. The results predicted using the models are compared with those obtained with the three-dimensional simulator Davinci to verify the accuracy of the proposed analytical models.

Dual-Material Surrounding-Gate Metal–Oxide–Semiconductor Field Effect Transistors with Asymmetric Halo

Asymmetrical halo and dual-material gate structure are used in the sub-100nm surrounding-gate metal–oxide–semiconductor field effect transistor (MOSFET) to improve the performance. Using three-region parabolic potential distribution and universal boundary condition, analytical surface potential and threshold voltage models of the novel MOSFET are developed based on the solution of Poisson's equation. The performance of the MOSFET is examined by the analytical models and the 3D numerical device simulator Davinci. It is shown that the novel MOSFET can suppress short channel effect and improve carrier transport efficiency. The derived analytical models agree well with Davinci.

Performance and analytical modelling of halo-doped surrounding gate MOSFETs

Halo structure is added to sub-100 nm surrounding-gate metal–oxide–semiconductor field-effect-transistors (MOSFETs) to suppress short channel effect. This paper develops the analytical surface potential and threshold voltage models based on the solution of Poisson's equation in fully depleted condition for symmetric halo-doped cylindrical surrounding gate MOSFETs. The performance of the halo-doped device is studied and the validity of the analytical models is verified by comparing the analytical results with the simulated data by three dimensional numerical device simulator Davinci. It shows that the halo doping profile exhibits better performance in suppressing threshold voltage roll-off and drain-induced barrier lowering, and increasing carrier transport efficiency. The derived analytical models are in good agreement with Davinci.

Capacitorless Dynamic Random Access Memory Cell with Highly Scalable Surrounding Gate Structure

We propose the surrounding gate metal oxide semiconductor field effect transistor (MOSFET) with vertical channel [surrounding gate and vertical channel (SGVC) cell] as a one transistor (1T) dynamic random access memory (DRAM) cell. To confirm the memory operation of the SGVC cell, we fabricated a highly scalable SGVC cell. Because of its vertical channel structure and common source architecture, it can readily be made into a 4F2 cell array. The sensing margin was around 6 µA which is sufficiently large for read operation. Read retention time was about 4 ms meaning that the read operation is non-destructive. Also, we have revealed that not only an increase in the volume of the floating body region but also an adequate amount of charge is required for an increase in the sensing margin.

Theory of Short-Channel Surrounding-Gate Metal–Oxide–Semiconductor Field-Effect-Transistors

A model for a metal–oxide–semiconductor field-effect-transistor (MOSFET) with a surrounding gate (SG) is developed. Analytical solutions to the model are obtained by solving Poisson's equation using series expansion. Taking short-channel effects into account, the analytical expressions for electric potential, electric field, and threshold voltage are obtained. It is found that the transistor is fully depleted for a small radius, and the threshold voltage increases as the radius increases or as the oxide capacitance per unit area decreases.

New Current–Voltage Model for Surrounding-Gate Metal–Oxide–Semiconductor Field Effect Transistors

On the basis of the current continuity equation and closed-form solutions of Poisson's equation, a new and continuous current–voltage (I–V) model that includes both doped and undoped Si bodies for surrounding-gate metal–oxide–semiconductor field effect transistors (MOSFETs) is developed. The continuous form of the I–V equation represents the entire drain current characteristics including all regions of MOSFET operation: linear, saturation and subthreshold. Compared with conventional charge-sheet approximation, this approach preserves physical volume-inversion phenomena and easily predicts drain current characteristics without assuming an empirical smoothing function for the correctness of piecewise approximation. It is shown that the I–V curves can be generated using this model and agree well with two-dimensional (2D) simulation results over various drain biases. This model gives the exact I–V prediction for surrounding-gate MOSFETs and can be used in SPICE simulation.

A Generalized Electrostatic Scale Length for Fully Depleted Surrounding-Gate Metal–Oxide–Semiconductor Field Effect Transistors

On the basis of the continuity of the electric flux and potential at the interface between a Si body and a gate insulator, and of the effective insulator thickness, a generalized electrostatic scale length for two-dimensional (2D) effects in fully depleted surrounding-gate (SG) metal–oxide–semiconductor field effect transistors (MOSFETs) is derived. It is found that for the same equivalent oxide thickness, a gate insulator with a higher dielectric permittivity results in stronger 2D effects caused by an increase in electrostatic scale length. Both a thin gate insulator and a thin Si body are required to realize a small electrostatic scale length to suppress short-channel effects. Compared with conventional planar MOSFETs, high-gate-permittivity SG MOSFETs theoretically can be designed such that its insulator is thicker than its Si body without increasing its electrostatic scale length. With appropriate modification of the effective insulator layer thickness, the model also indicates an increased scale length due to quantum effects.

Concise Analytical Threshold Voltage Model for Cylindrical Fully Depleted Surrounding-Gate Metal–Oxide–Semiconductor Field Effect Transistors

On a basis of a quasi-2D potential analysis using the effective conducting path effect (ECPE), a concise analytical model for the threshold voltage in cylindrical fully depleted surrounding-gate (SG) metal–oxide–semiconductor field effect transistors (MOSFETs) is derived. With various depths of the effective conducting path, the minimum channel potential Φdeff,min induced by ECPE is used to develop the threshold voltage model. Besides the increased depth of the effective conducting path, a thin silicon body and a decreased oxide thickness can reduce threshold voltage roll-off simultaneously. It is also observed that the threshold voltage shift depends on the scaling factor. A large scaling factor is preferred to alleviate threshold voltage degradation. This paper not only provides a simple analytical model but also offers an efficient analysis of the threshold voltage of the short-channel cylindrical fully depleted SG MOSFETs.