Synthesis and photocatalytic activities of MnO 2-loaded Nb 2O 5/carbon clusters composite material

Low-cost preparation method for exposing IC surfaces in stacked die packages by micro-abrasive blasting

In this paper, new inspection method is proposed for the surfaces of lead frame and IC's. Optimal optical system and the accurate algorithm for the surface inspection are needed in machine vision area. The proposed optical system is composed of rectangular oblique light illumination and coaxial light illumination for the higher contrast and the results shows the better performances through experiments. The markings of IC surface are inspected using the accurate proposed method using the partitioned correlation coefficient, and the result shows reduction of under kill ratio compared to the previous method.

Development of a novel GaAs micromachined accelerometer based on resonant tunneling diodes

ABSTRACT In the realm of three-dimensional (3-D) integration, through-wafer interconnections using through-silicon vias (TSVs) for wafer-level 3-D integration and stackable IC packaging are receiving more attention because TSVs help to increase the interconnect density, decrease wire lengths, and save space. These effects lead to high performance, low power requirements, and smaller electronic gadgets. TSVs are created mainly using dry-etch processes [1], [2], laser drilling [3], and wet-etch processes [4]. The dry-etch process provides fine-pitch and high-aspect-ratio via holes, while the wet-etch process provides an economic alternative through batch processing and is easier for subsequent metallization due to tapered via structure and smooth via surface along the [111] crystalline plane. Traditionally, silicon nitride deposited by plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) has been used as an etch mask during the wet-etch process using potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH). The silicon nitride etch mask presents several disadvantages, e.g., it forms pinholes, blisters during the etch process, has a high deposition temperature, and presents a high cost. Presented here is a novel process using a photosensitive (negative acting), spin-applied, organic polymer etch protective coating1 that could potentially replace silicon nitride and other metals as an etch mask for wet-etch processes using potassium hydroxide (KOH) or tetramethyl ammonium hydroxide (TMAH) [5]. The coating is spin coated onto the wafer, and a standard photolithography technique is used to create the mask pattern/image on the backside of the wafer. The IC surface side of the wafer could also be protected with a blanket of etch protective coating. In this paper, we have compared the etch protection characteristics of the photosensitive material to LPCVD silicon nitride. Wet-etch tests were done at varying etch times for the formation of vias. A comparison of undercut between the silicon nitride protection and the photosensitive coating protection was conducted to show that ratio of undercut to depth for the photosensitive etch protective coating is constant for stable etching conditions. Effects of other factors such as etch bath concentration and temperature and etch time are also examined.

The properties of supercooled liquid water and the mechanism of crystallization in it were investigated using time-of-flight secondary ion mass spectrometry and reflection absorption infrared spectroscopy. The self-diffusion of the water molecules commences at 136 K, and then the liquid-liquid phase transition occurs at 160-165 K. The latter is evidenced not only by the occurrence of fluidity but also by the formation of a LiCl solution. The infrared absorption band also changes drastically above 160 K due to crystallization of water (on the Au film) and the formation of LiCl solution (on the LiCl film). The immediate crystallization and dissolution of LiCl are thought to be characteristic of normal water that is created in a deeply supercooled region, indicating that viscous liquid water (T > 136 K) is transformed into supercooled liquid water at around 160 K. The crystallization kinetics is different between these two phases because the former (latter) involves nuclear growth (spontaneous nucleation). Without nuclei, crystallization is quenched below 160 K in the present experiment. It is suggested that the viscous liquid phase coexists at the surface or grain boundaries of metastable ice Ic.

In the applications of 3-D packages or stacked die packages, mostly the silicon wafers have to be ground thinner, and then the strengths of the dies from the wafers are needed for assuring good design and reliability of the packages. The purposes of this study are twofold: one is to attempt to develop a new, suitable test method for differentiating the factors that affect the variability of die strength, and the other is to investigate the failure and fatigue strengths of silicon dies. In this paper, a new test method, a plate-on-elastic-foundation test (PEFT) associated with point- or line-loading has been proposed and evaluated. It is found that the PEFT can provide not only a simple, chipping-free test for dummy or real IC chips without limitation of size, but also a (bi-axial) stress field similar to the temperature loading. The strength data of failures on IC and ground surfaces in real IC chips are presented. The good consistency of the die strength data with a minor scatter from both the point- and line-load tests is found for the specimens failed on IC surfaces, but not for the ones failed on the ground surfaces. The inconsistency of strength data from both tests for failure on ground surfaces is due to edge chipping involved. The large scatter is caused by the combined factors of the angle of grinding marks, planes of weakness of material, and loading stress states with uni-axial stress for line-load test and with unequal bi-axial stress for point-load test of rectangular specimens. The surface roughness of the dies (including the IC and ground surfaces) measured by atomic force microscopy is correlated with the failure modes and strengths from the tests. It is found that the silicon die strengths are dominated by the roughness on failure surfaces, and their failure modes always appear cracks along the directions parallel and normal to the edges of the die, which might be the weak plane of the crystal lattice of silicon. The specimens with artificial cracks have been further tested. It has been proved that the die strength dominated by the crack initiation depends on the most severe defect but not on the amount of the defects, and its failure mode is controlled by a special weak plane after the crack initiation. Conclusively, there are four factors to influence die strength: the surface conditions of the die (including grinding-mark direction and surface roughness), the edge crack of the die (so-called chipping created during the cutting process), the weak planes of the crystal lattice of silicon, and, sometimes, different tests with various loading conditions. The fatigue strength of the die is also determined to be about 25% lower than the static one.

This paper presents a novel type of hybrid dispensing head for IC fabrication and surface mount technology. The proposed mechanism consists of solenoid valve and piezoelectric stack as actuators, and provides positive-displacement and jet dispensing. The positive-displacement dispensing can produce desired adhesive amount without viscosity effect, while the jet dispensing can produce high precision adhesive amount. In order to determine the relationship between required voltage of the piezoelectric actuator and needle displacement, both static and dynamic analysis are undertaken, In addition, finite element analysis is performed in order to find optimal design parameters. Dispensing flow rate and pressure in the chamber are evaluated through fluid dynamic model.

Impact of semiconductors material on IR Laser Stimulation signal

Fine-tuning of helper T cell activation and apoptosis by antigen-presenting cells

Fine-tuning of helper T cell activation and apoptosis by antigen-presenting cells

During IC inspection, which includes the two parts of Mark and Lead, the deviation of IC on the tape occurring in high speed movements usually generates light reflection effect, which in turn causes errors in IC recognition as measured by machine vision system. this research filters the light reflection effect by developing standard components, identifies the correct position of IC Lead, hence fixes the measurement errors or non‐measurability caused by light reflection, avoids the resulting discontinued operation of measuring system, and improves the productivity.

The order of the relative degree of iron oxide coating of 4 samples of red soils from north-eastern Argentina was established using the point of zero charge (PZC), yielded by potentiometric titration, and the isoelectric point (IEP), obtained from the diffusion potential. When PZC is different from IEP, the relative fraction of apparent surface coverage could be assessed from the IEP. The results obtained by the application of X-ray diffraction, scanning electron microscopy, electron probe microanalysis, X-ray photoelectron spectroscopy, Mössbauer spectroscopy, and specif ic surface area, although essential to characterise the samples, did not allow us to determine the degree of iron oxide coating. Our findings show that the order of this degree is opposite to the order of the ratio of the amount of free iron oxides to that of clay in iron oxides/clay mixtures.

The self-heating of Si devices operating in the 4 K<T<300 K range is discussed in this work. The temperature-dependent thermal time constant of a typical Si chip is calculated and compared to several electrical relaxation times. Thermal events may be indistinguishable from electrical events at low temperatures, and this makes the transient method an unreliable one for characterizing the cryogenic self-heating. A semi-analytical approach, which considers the temperature dependence of the thermal conductivity of Si, is used to calculate the steady-state thermal profile on the top surface of a Si IC where a device is dissipating power at different ambient temperatures. Theoretical results indicate that the temperature rises measured in earlier works cannot be due to the thermal properties of Si at low temperatures. A test chip containing several integrated Si devices is used to characterize experimentally the self-heating. The strong self-heating usually observed in Si devices operating at very low temperatures is dominated by the parasitic thermal resistance, of which the ceramic package is the main contributor. The dominance of this parasitic contribution decreases for an increasing ambient temperature and becomes similar to that of the Si device at 300 K.

Failure analysis method by using different wavelengths lasers and its application

This paper describes the development of a new kind of two-dimensional high-resolution imaging integrated circuit. It is used in conjunction with micro-channel plate (MCP) electron multipliers. The electron detection array IC (EDAIC) consists of a two-dimensional array of charge sensing circuits each covered by its own m aluminium electrode on the IC surface. These electrodes are used to collect electronic charge from the MCP channel outputs. The sensors are arranged and accessed in a DRAM-like manner and can be configured to generate either an analogue or a digital output. The EDAIC device is a multiple, simultaneous, event detector suitable for medium-count-rate applications and was originally developed for use in an x-ray photoelectron spectrometer.

The routing of interconnections along the surface of a high-voltage IC presents one of the major issues for the IC designer. A special problem appears, if the interconnection can stay under a high-voltage signal and has to cross the boundaries of p-n junctions. In this paper, the influence of a high-voltage interconnection (HVI) on the blocking capability of a planar p-n junction including a JTE-design is investigated numerically by solving Poisson's equation under the depletion approximation. Recent 2-D simulations have shown, that a HVI crossing the space charge region within a distance smaller than 5 /spl mu/m reduces the breakdown voltage drastically. However, these calculations ignored the limited lateral extension of real interconnection stripes and tend to overestimate its influence. As exhibited by the 3-D simulations in this paper, the influence of the stripe width can be ignored only for such structures, where the width of the stripe is in the same order of magnitude as the depletion layer width. For smaller stripe widths the influence of the HVI is lower. The dependence of the breakdown voltage on the stripe width is investigated for different distances between the HVI and the semiconductor surface.

Abstract The purpose of this paper is to develop an automatic IC chip inspection and recognition system. This vision system can find the pins in an IC chip and then determine its major axis precisely. Based on the rules developed in this study, the system can successfully detect the label blocks printed on the IC surface. An algorithm for dividing merged characters within a block has also been established. The features of the characters are constructed from stroke relationship and their pattern profile. A fuzzy‐neural network is used to classify the symbols and determine the orientation of IC chips. Finally, the system can combine them into meaningful data and recognize the symbols.

Results of critical stress intensity factor, K IC , and fracture surface energy, Γ, measurements for composite where the SiO 2 sonogel matrix obtained from TEOS (tetraethoxysilane) is combined with fine SiO 2 particles (Aerosil) which form the dispersed phase, are presented

ABSTRACTWe present fast, wafer-scale imaging of the surface charge achieved via non-contact measurement of the surface potential barrier by surface photovoltage (SPV) under high excitation levels. The approach is capable of resolving surface charge differences as small as 108 q/cm2. Fundamentals of surface charge imaging are discussed, and the method is compared with standard SPV contamination mapping. Examples include problems relevant to silicon IC fabrication and surface charge maps of GaAs and InP.