Surface Mount Process Research Articles

Reactive extrusion for efficient preparation of high temperature resistant PA6T/66/BN composites with great thermal management and mechanical properties

High temperature resistant polymer-based composite with high thermal conductivity and great mechanical properties are highly demanded in the field of electronic devices for simultaneously meeting surface mounting process and high-power operation. The key to achieving this goal is to balance the contradiction between the high melt viscosity of high-temperature resistant polymers and the dispersibility of fillers. In this work, the high-performance polyamide 6T/66/hexagonal boron nitride (PA6T/66/BN) composites were fabricated successfully via the method combining prepolymerization and reactive extrusion. Results demonstrated that this method not only significantly improves the preparation efficiency of high temperature resistant polyamide and its composites, but also enables the prepared composites to reach 3.6 W/(m⋅K), over 299 °C and 67.8 MPa in thermal conductivity, melting point and tensile strength respectively. Furthermore, the prepared composite exhibits excellent thermal management effects on LED and CPU. Therefore, the results of this work are of great significance for the efficient preparation and wide application of high-temperature resistant polymer based thermally conductive composites.

Evaluation of Residual Stress in MEMS Micromirror Die Surface Mounting Process and Shock Destructive Reliability Test

Light Detection and Ranging (LiDAR) devices based on Micro-Electro-Mechanical Systems (MEMS) micromirrors have been promising sensors for automatic driving owing to the advantages of MEMS devices. The packaging plays a vital role in the reliability of MEMS micromirror but introduces the residual stress from the surface mounting process. The shock reliability of micromirrors is influenced by residual stress. In this work, the residual stress from the surface mounting process are investigated through resonant frequency tests. The frequency drift can be 718 Hz and -281 Hz under the residual stress of 107.0 MPa and -25.0 MPa respectively. As the difference of CTE rises, the residual stress proportionally increases but decreases with the thickness of the substrate. In addition, a higher curing temperature can introduce a more significant stress level. The dynamic response in shock environment under different residual stress are analyzed. Drop fall experiments verify the theoretical conclusions that the stiffness hardening effect can improve the shock level tolerance. The tensile stress levels of 41.7 MPa and 107.0 MPa are corresponding to 100 g and 200 g respectively. The influences of residual stress on frequency drift and reliability need to be considered seriously and simultaneously during the packaging design for MEMS micromirrors. This work provides a deep insight into commercial applications of MEMS-based LiDAR in autonomous driving.

A Drop-In High-Temperature Pb-Free Solder Paste That Outperforms High-Pb Pastes in Power Discrete Applications

Sn-based high-temperature Pb-free (HTLF) solder pastes have been developed as a drop-in solution to replace high- Pb solder pastes in power discrete applications. The pastes were designed with Indium Corporation’s DurafuseVR technology, to combine the merits of two constituent powders. A SnSb-based Ag/ Cu-containing high-temperature powder, with a melting temperature above 320 degrees C, was designed to maintain high-temperature performance. A Sn-rich SnAgCu-Sb powder, with a melting temperature around 228 degrees C, was added to the paste to enhance wetting and improve joint ductility. In the design, the final joint will have the low-melting phase (the melting temperature >228 degrees C) in a controllable quantity embedded into the high-melting SnSb matrix. HTLF-1, one of the designs, maintained the bond shear strength up to 15 MPa, even around 290 degrees C. Another design, HTLF-2, has a similar bond shear strength as Pb92.5/Sn5/Ag2.5 around 290 degrees C, but exceeds substantially below 250 degrees C. The power discrete components had been built with both HTLF solder pastes for both die-attach and clip-bond through the traditional high-Pb process, which demonstrated the drop-in processing compatibility. The components survived three additional surface mounting (SMT) reflows (peak temperature upto 260 degrees C) and passed moisture sensitivity level 1 (MSL1). This confirmed that the maintained joint strength (comparable to or stronger than high-Pb), helped to keep the joint integrity within the encapsulated components in the following SMT process, even with the controlled quantity of the melting phases above 228 degrees C. Both HTLF solder pastes outperformed Pb92.5/Sn5/Ag2.5 in the resistance from drain to source when power is on (RDS(on)), even after 1,000 cycles of temperature cycling test (TCT) under 255/175 degrees C, which is attributed to the intrinsic lower electrical resistivity of Sn in both HTLF pastes. Microstructural observation had shown no corner cracks for both die-attach and clip-bond joints after TCT.

Research on Printing Defects Inspection of Solder Paste Images

Solder paste printing is the first part of the surface mount process flow; its postprinting defect inspection is particularly important. In this paper, we focus on studying the printing defects inspection algorithm for solder paste on PCB (Printed Circuit Board) images. The work proposes a number of methods to enhance the defects inspection performance of solder paste printing: a regional multidirectional data fusion image interpolation method, which can achieve fast and high precision image interpolation; a method for detecting solder paste areas with better accuracy, efficiency, and robustness; an improved connected domain labeling method to reduce time complexity; and defects detection and types classification method, which extracts features and centroid of every solder paste region and completes the inspection by comparing with a standard image. The experiments show that the defects inspection algorithm can detect the most common types of defects with low time consumption, high inspection accuracy, and classification accuracy.

Investigation of solder beading phenomenon under surface-mounted electrolytic capacitors

PurposeThe purpose of this paper is to study the solder beading phenomenon (referring to larger-sized solder balls) of surface-mounted electrolytic capacitors. Solder beading could induce failures by violating the minimal electrical clearance on the printed circuit board (PCB). In modern lead-free reflow soldering, especially in high-reliability industries, such as automotive, aeroplane and aerospace, detecting and preventing such defects is essential in reliable and cost-effective manufacturing.Design/methodology/approachThe large size of the involved components may block the view of automatic optical inspection; therefore, X-ray inspection is necessary. To detect the failure mode, X-ray imaging, cross-section grinding, optical microscopy and Fourier transformed infrared spectroscopy were used. High-resolution noncontact profilometry and optical microscopy were used to analyse component designs. The surface mounting process steps were also analysed to reveal their dependence on the issue. Test methods were designed and performed to reveal the behaviour of the solder paste (SP) during the reflow soldering process and to emphasise the component design relevance.FindingsIt was found that the reduction of SP volume only reduces the failure rate but does not solve the problem. Results show that excessive component placement pressure could induce solder beading. Statistical analysis revealed that differences between distinct components had the highest effect on the solder beading rate. Design aspects of solder beading-prone components were identified and discussed as the primary source of the problem.Practical implicationsThe findings can be applied in surface-mount technology production, where the total failure count and resulting failure costs could be reduced according to the findings.Originality/valueThis paper shows that component design aspects such as the low distance between the underside of the component and the PCB and blocked proper outgassing of volatile compounds of the SP can be root causes of solder beading under surface-mounted electrolytic capacitors.

Low-Density Fan-Out Heterogeneous Integration of MEMS Tunable Capacitor and RF SOI Switch

Abstract Using Low-Density Fan-Out (LDFO) packaging technology, a radio frequency (RF) microelectromechanical systems (MEMS) tunable capacitor array composed of electrostatically actuated beams on 180nm high-voltage CMOS silicon was heterogeneously integrated with a single-pole four-terminal (SP4T) RF switch on 180nm CMOS silicon-on-insulator (SOI). The primary objective of this study was to determine the manufacturability of this System-in-Package (SiP) design, which is proven at time zero through survival of the MEMS device based on acceptable MEMS performance metrics. In addition, the RF SOI switch provides high-voltage electrostatic discharge (ESD) protection for the MEMS device. Capacitive MEMS structures are particularly sensitive to unpredictable electrostatic charging scenarios, such as handling after package assembly and printed circuit board (PCB) surface mount processing. Consequently, resistance to dielectric breakdown by means of robust ESD protection is a very desirable quality. Integrating the RF switch in close proximity with the MEMS device not only enables the ability to withstand charging scenarios in excess of 1kV (human body model), it mitigates the impact of parasitics on RF performance by minimizing interconnect lengths and complexity.

Effect of temperature on the fracture behavior of Cu/SAC305/Cu solder joints

Double cantilever beam (DCB) specimens consisting of Sn96.5Ag3.0Cu0.5 (SAC305) solder sandwiched between two copper bars were fabricated under standard surface mount processing conditions. Mode-I fracture tests were performed on the DCB specimens under various temperatures. The load–displacement behavior and critical loads corresponding to crack initiation were recorded and used in a finite element model of the DCB to evaluate critical energy release rates. Fracture surfaces were analyzed to understand the effect of temperature on crack path and fracture mechanism. The critical energy release rate decreased from 603 at −50 °C to 93 J/m2 at 100 °C and the crack path shifted from solder/intermetallic compound interface to bulk solder.

A Module-on-module Manufacturing Process and the Study of its Warpage and Signal Integrity

This paper describes a package design and associated manufacturing assembly process that stack a module on top of another module using a frame board. The module on the top could be in molded or open frame form. In addition, this manufacturing process is compatible with the conformal shielding process important in RF applications. The complete module-on-module can be coated seamlessly and connected to the ground planes of the two substrates. The module may be a part of product line that requires more functionality over the same foot print. There is the need to houses more components than its predecessor. Such example includes the standard memory package-on-package. However, if the module on top is not of commodity type, or when the volume is not big enough to develop a standard package, this module-on-module architecture and process could be a good solution. Alternatively, one could fix the design of bottom module , and design multiple choices of the top module. When stacked together, the two modules form various different configurations in order to serve different functionalities. The structure of the module on module is shown in figure 1 below: Figure 1 Structure of the Module on Module On the frame board, there are vertical via where vertical electrical and power connection can be made. The frame board is mounted on the main board-II by surface mount process with underfill option. In the figure, a molded module on the top is shown, and an overall coating is applied to the whole module-on-module. Figure 2 Manufacturing Process of the Module-on-module The assembly process of the module-on-module is shown in Figure 2. First, the bottom module is manufactured by a one side SMT process and sawed, with the frame board soldered and underfilled. Then, the top module is SMT and molded in a panel form on the one side, and the bottom module is SMT and underfilled on the other side. Last, the complete module is sawed and conformal shielded by the sputtering process. The design of the ground plans of the substrates, together with that of the frame board, makes it such that the coating is connected to the ground planes of the boards. It is important to study the warpage of such a module-on-module to make sure that it meets the JDEC standards. It is important to assure that the signal integrity of the electrical connections, including RF connections, inside of the frame board meets the requirement. Both simulation and measurement are made to test vehicles of the module-on-module. It is found that the simulation matches the measurement nicely. This module structure can be used for a variety of applications.

Surface Mounting Process Using Hybrid Resin Sheet Including Self-Organizable Solder Particles

Surface Mounting Process Using Hybrid Resin Sheet Including Self-Organizable Solder Particles

Color Biological Features-Based Solder Paste Defects Detection and Classification on Printed Circuit Boards

Deposited solder paste inspection plays a critical role in surface mounting processes. When detecting solder pastes defects on a printed circuit board, profile measurement-based methods suffer from large system size, high cost, and low speed for inspection, although they provide 3-D information of solder pastes. In contrast, image analysis-based methods facilitate the defect detection process of solder pastes by treating them as a pattern recognition problem. However, existing image analysis methods do not perform well because low-level visual features cannot catch sufficient information for defect detection. This paper proposes a new defect detection scheme for solder pastes based on learning the color biological feature sub-manifold. In particular, we apply the biologically inspired color feature (BICF) to represent the solder paste images, and introduce a new sub-manifold learning method to extract the intrinsic low-dimensional BICF manifold embedded in an extrinsic high-dimensional ambient space. This scheme mimics the function of human visual cortex in recognition tasks, and can separate poor quality solder pastes from good quality ones. We apply the new scheme to our automated optical inspection system, and thorough empirical studies indicate the effectiveness of the new scheme for practical utilization.

Effects of High-Temperature Treatment on the Reaction Between Sn-3%Ag-0.5%Cu Solder and Sputtered Ni-V Film on Ferrite Substrate

We have demonstrated a novel sputtering method for lead-free thin metal films on ferrite substrates for surface-mount inductor applications. In a surface-mounting process, the cladding of enameled wire needs to be burnt off at high temperature, which requires the devices to withstand a high-temperature reliability test at 420°C for 10 s. There are no reports that a sputtered film of thickness less than 6 μm can withstand this test. In this work, we used Ag/Ni-7 wt.%V double metal layers for the metallization. The dissolution of Ni-7 wt.%V in Sn-3%Ag-0.5%Cu lead-free solder at various temperatures was studied in detail. Scanning electron microscopy with energy-dispersive x-ray spectroscopy was used to investigate the interfacial reaction between the sputtered films and the solder. The intermetallic compounds are mainly (Cu,Ni)6Sn5 at 250°C; however, (Ni,Cu)3Sn4 becomes the predominant composition at 420°C. In addition, although outdiffusion of V atoms from the Ni-V layer was observed, its effect on the intermetallic compound (IMC) was insignificant. We further confirmed that the proposed metallization is able to pass the aforementioned high-temperature reliability test.

The Application of Two-Dimensional X-ray Hot Stage in Flip Chip Package Failure Analysis

Advancement of silicon and packaging technologies toward lower power and higher functionality requires better understanding between materials and process interactions. This paper illustrates the applications of 2-D X-ray metrology incorporated with a hot stage system for the first time in the literature, which allows one to simulate heating profiles of up to 300°C and observe the behavior of materials in situ within the packages. Three case studies are discussed: 1) segregation of metal particles in the next-generation thermal interface material, leading to corner thermal resistance (Rjc) degradation; (2) first level interconnect (FLI) solder bump bridging during chip attach of a large die server package with high substrate die area warpage in which limits of the die area substrate warpage need to be set in order to avoid FLI solder bump bridging during the chip attach solder reflow process; and 3) second level interconnect solder joint bridging at the surface mounting process of a large die package attached with an integrated heat spreader. By being able to study failures in situ at high temperatures, a new dimension to the package failure analysis is presented in this paper.

Effect of geometry on the fracture behavior of lead-free solder joints

Copper bars were soldered along their length with a thin layer of lead-free Sn3.0Ag05.Cu alloy under standard surface mount processing conditions to prepare double cantilever beam (DCB) specimens. The geometry of the DCBs was varied by changing the thickness of the solder layer and the copper bars. These specimens were then fractured under mode-I and two mixed-mode loading conditions. The initiation strain energy release rate, G ci , increased with the relative fraction of mode-II, but was unaffected by the changes in either the substrate stiffness or the solder layer thickness. However, the steady-state strain energy release rate, realized after several millimeters of crack growth, was found to increase with the solder layer thickness at the various mode ratios. The crack path was found to be influenced by mode ratio of loading and followed a path that maximizes the von Mises strain rather than maximum principal stress. Finally, some preliminary results indicated that the loading rate significantly affects the G ci .

Processing and Reliability Assessment of Silicon Based, Integrated Ultra High Density Substrates

High density interconnect (HDI) advances in substrate technology have allowed considerable improvements in processing more complex, compact devices. Chip Scale Packaging (CSP) and multi-chip modules (MCM) have continued to decrease in size and increase in functionality, moving closer to be more like flip chip technology. Improvements in wafer structuring allow for tremendous possibilities for device functionality; however a limit does exists on what traditional substrate fabrication methods will allow. A push in developing through silicon vias (TSVs) and use of alternative materials, other than organic or flex, are needed to enable new packaging technology developments. As needed, an alternative substrate has been developed that uses Silicon-based technology, photo-defined vias and the capability of semiconductor level routing density. It also includes the possibility to open cavities in the substrate to embed integrated die. This technology has opened up many possibilities for fabricating Ultra high density substrates from a US-based supplier that enables the use of integrated die, surface mount processing and fine pitch, multi-die placements. The following paper details the processing and reliability capabilities of this substrate technology. A comprehensive characterization study was conducted to evaluate the processing of units containing ultra-small SMT devices, intermixed with fine pitch, flip chip die. The units were also processed with traditional BGA balling, making them compatible with level 2, PCB level processes. Data will be shown with the results of the assembly analysis and subsequent reliability assessment of these units, showing a robust performance with thermal shock, uHAST and MSL level testing. A full analysis of the substrates structure will also be shown. The paper will show this technology's possibilities as a next generation substrate alternative.

Fracture load prediction of lead-free solder joints

Abstract Continuous and discrete SAC305 solder joints of different lengths were made between copper bars under standard surface mount (SMT) processing conditions, and then fractured under mode-I loading. The load–displacement behavior corresponding to crack initiation and the subsequent toughening before ultimate failure were recorded and used to calculate the critical strain energy release rates. The fracture of the discrete solder joints was then simulated using finite elements with two different failure criteria: one in terms of the critical strain energy release rate at initiation, G ci , and another based on a cohesive zone model at the crack tip (CZM). Both criteria predicted the fracture loads reasonably well. In addition, the CZM was able to predict accurately the overall load–displacement behavior of the discrete joint specimen. It could also predict the load sharing that occurred between neighboring solder joints as a function of joint pitch and adherend stiffness. This has application in the modeling of the strength of solder joint arrays such as those found in ball grid array packages.

Mixed-mode fracture load prediction in lead-free solder joints

Abstract Double cantilever beam (DCB) fracture specimens were made by joining copper bars with both continuous and discrete SAC305 solder layers of different lengths under standard surface mount (SMT) processing conditions. The specimens were then fractured under mode-I and various mixed-mode loading conditions. The loads corresponding to crack initiation in the continuous joints were used to calculate the critical strain energy release rate, J ci , at the various mode ratios using elastic–plastic finite element analysis (FEA). It was found that the J ci from the continuous joint DCBs provided a lower bound strength prediction for discrete 2 mm and 5 mm long joints at the various mode ratios. Additionally, these J ci values calculated from FEA using the measured fracture loads agreed reasonably with J ci estimated from measured crack opening displacements at crack initiation in both the continuous and discrete joints. Therefore, the critical strain energy release rate as a function of the mode ratio of loading is a promising fracture criterion that can be used to predict the strength of solder joints of arbitrary geometry subject to combined tensile and shear loads.

Process and pad design optimization for 01005 passive component surface mount assembly

PurposeThe ever present need for the miniaturization of electronic assemblies has driven the size of passive components to as small as the 01005 package size. However, the packaging standards for these components are still under development. The purpose of this work is to report results from experiments designed to establish optimum process parameters, pad sizes and component clearances for the surface mounting of 01005 passive components.Design/methodology/approachThe experiments were designed using MODDE, an experimental design software tool, and were carried out with both 01005 capacitors and resistors. All the assembled components were examined under microscope and judged according to industrial workmanship standards.FindingsIt was found that a viable solder paste printing process for the assembly of 01005 components can be achieved with a 75 μm thick stencil. Type 5 solder paste achieved a similar printing performance to type 4. Under the experimental conditions used, the optimum pad dimensions for the 01005 capacitors were 210 μm length, 220 μm width, 160 μm separation and for the resistors were 190 μm length, 220 μm width, 160 μm separation. The smallest component clearance to reliably avoid bridging was found to be 100 μm. A high placement force of 3.5 N was found to cause cracking of 01005 resistors.Originality/valueFrom this work, a surface mount process for 01005 passive components is established and it is concluded that electronics packaging density can be increased through the assembly of these small components. In the near future, the widespread use of them will definitely facilitate a further reduction in the size of electronic assemblies, especially in handheld and portable devices.

Quality control of semiconductor packaging based on principal components analysis

5 critical quality characteristics must be controlled in the surface mount and wire-bond process in semiconductor packaging.And these characteristics are correlated with each other.So the principal components analysis(PCA) is used in the analysis of the sample data firstly.And then the process is controlled with hotelling T~2 control chart for the first several principal components which contain sufficient information.Furthermore,a software tool is developed for this kind of problems. And with sample data from a surface mounting device(SMD) process,it is demonstrated that the T~2 control chart with PCA gets the same conclusion as without PCA,but the problem is transformed from high-dimensional one to a lower dimensional one,i.e.,from 5 to 2 in this demonstration.

Full-Field 3-D Measurement of Solder Pastes Using LCD-Based Phase Shifting Techniques

Quality inspection of deposited solder pastes is critical in surface mounting processes. As surface-mount technology (SMT) component pitches decrease, three-dimensional (3-D) measurement of solder pastes has become more and more important in ensuring solder joint reliability. Currently, the 3-D measurements for solder pastes are mainly performed by laser-based systems. However, they suffer from low inspection speed due to the physical line-scanning process. In this paper, a fast and cost-effective 3-D measurement system for deposited solder pastes is proposed. The proposed system uses a liquid crystal display (LCD)-based phase shifting technique to perform full-field 3-D measurement of solder pastes with high accuracy. Experiments have shown that the 3-D profiling and volume measurement of solder pastes are very efficient and effective with the proposed system. The volume measurement repeatability is in the micrometer range. The processing time of the proposed 3-D measurement system for an image of 640/spl times/480 pixels is less than 1 s on a typical personal computer.

Application of Surface Mount Processes for Economical Production of High-Aspect-Ratio Microchannel Arrays

This paper reports on the feasibility of using surface mount technology (SMT) assembly processes and materials to produce highly parallel, high-aspect-ratio microchannel arrays. Experimental results show that the fabrication of high-aspectratio (> 40:1) microchannel arrays is possible using solder paste screen printing and reflow bonding. A simple model and empirical examination verifies that very little solder is wicked into the channel during reflow. The use of low bonding temperatures (under 300°C) and pressures results in well-aligned, parallel channels with low levels of warpage. Channel height variation within these microchannel arrays was measured to be less than ±1.2% of the overall mean channel height of 270.9 μm. Gravity effects on three-channel devices were found to be insignificant. The microlaminated devices were found to tolerate an air pressure of 1.72 bar (25 psi) without leakage, though it is expected that higher air pressures are possible as the devices were not tested to failure.