Surface Mount Technology Process Research Articles

The preparation and wettability of the Sn-9Zn-2.5Bi-1.5In solder paste for SMT process and high shear ball performance

Purpose This study aims to focus on the surface mount technology (SMT) mass production process of Sn-9Zn-2.5Bi-1.5In solder. It explores it with some components that will provide theoretical support for the industrial SMT application of Sn-Zn solder. Design/methodology/approach This study evaluates the properties of solder pastes and selects a more appropriate reflow parameter by comparing the microstructure of solder joints with different reflow soldering profile parameters. The aim is to provide an economical and reliable process for SMT production in the industry. Findings Solder paste wettability and solder ball testing in a nitrogen environment with an oxygen content of 3,000 ppm meet the requirements of industrial production. The printing performance of the solder paste is good and can achieve a printing rate of 100–160 mm/s. When soldering with a traditional stepped reflow soldering profile, air bubbles are generated on the surface of the solder joint, and there are many voids and defects in the solder joint. A linear reflow soldering profile reduces the residence time below the melting point of the solder paste (approximately 110 s). This reduces the time the zinc is oxidized, reducing solder joint defects. The joint strength of tin-zinc joints soldered with the optimized reflow parameters is close to that of Sn-58Bi and SAC305, with high joint strength. Originality/value This study attempts to industrialize the application of Sn-Zn solder and solves the problem that Sn-Zn solder paste is prone to be oxidized in the application and obtains the SMT process parameters suitable for Sn-9Zn-2.5Bi-1.5In solder.

Toward Industry 4.0 in Surface Mount Technology: Smart Manufacturing in Stencil Printing Operations

As the foremost point of contact in surface mount technology (SMT) operations, the stencil/solder paste printer (SPP) is a major contributor to assembly defects in the printed circuit board (PCB) fabrication process. Initial printing defects lead to reductions in throughput, quality and reliability of the entire downstream system. Because of the high variation in SMT processes, a predictive, real-time machine learning (ML) algorithm to optimize printer settings based on the estimation of printing volumes is a promising solution to improving production performance and process capability. Building upon existing literature, this research discusses the implementation of a lab-trained ML model to predict optimal printing parameters and reduce changeover time within SPP processes through the training and testing of large solder paste inspection (SPI) datasets. To sustain growing market demand for smart electronics manufacturing (SEM), successful development and validation of a dynamic prediction system for optimizing printing parameters provides significant potential for improvements in first pass yield rates and system throughput.

Development and validation of a digital twin framework for SMT manufacturing

Electronics manufacturing is a global industry and key to innovation in the virtual world because it is the physical backbone. The cost-effective development and manufacture of such electronic modules are critical to maintaining the competitiveness of high-wage manufacturing countries. Therefore, two approaches suggest themselves: Design for Manufacturing (DfM) and manufacturing optimization. To apply both approaches in industry, it is necessary to introduce models that describe the relationship between process input and process output. Applied to electronics manufacturing processes, this means that design, process parameters, and material properties must be mapped to process quality criteria in end-of-line testing. Recently, machine learning (ML) algorithms have been emerging and dominating other modeling methods such as numerical simulation. To develop such complex ML models, a unified data structure for each input and output must be defined. This paper proposes an extensible ML-enabled framework that provides direct and structured access to the printed circuit board (PCB) design and process parameters. This framework is used to perform structured data acquisition using a custom data mining board. During the manufacturing of these PCBs on a full surface mount technology (SMT) process line, all available process machine-level data is collected, archived, and parsed into a uniform, standardized, and flat data structure. This enables fast analysis of the correlation between inputs and quality criteria, direct access by ML algorithms, and training of models. Through these measures, the quality of the framework is validated and correlations are revealed and compared to previous literature. This shows the great importance of a data framework for the integration of data analysis technologies into industrial processes.

Improving the sensitivity of statistical process monitoring of manifolds embedded in high-dimensional spaces: The truncated-Q statistic

We address the limitations of applying the well-known Q/SPE statistic for statistical process monitoring (SPM) on manifolds embedded in high-dimensional systems. Our analysis considers scenarios where the number of samples used for deriving the control limits during Phase I analysis is small regarding the number of variables to monitor, which is the prevalent situation in modern industry. After diving into the root causes of some problems associated with the implementation of SPM in large-scale processes, we propose an alternative residual statistic, called the truncated-Q statistic (QΔ) and the associated control limit. The sensitivity of the new statistic for sensor faults is analyzed through a Monte Carlo study involving processes of different dimensionalities and correlation structures, under different testing conditions. A significant improvement in detection sensitivity is observed, especially when the dimensionality of the process is high and the faults have low magnitudes and only affect a few sensors. The practical relevance of this finding is discussed in the paper and further corroborated with a real case study from an industrial Surface Mount Technology (STM) process. The truncated-Q statistic, whose code is made available, can be readily extended to linear and non-linear manifolds embedded in high-dimensional systems.

Rapid fault cause identification in surface mount technology processes based on factory-wide data analysis

Surface mount technology is an important process in modern electronic circuit manufacturing. Quality control problems have arisen in this area because of the increased design and processing complex...

Correlation of Warpage Distribution With the Material Property Scattering for Warpage Range Prediction of PBGA Components

In recent years, due to the increased size of ball grid array (BGA) devices, the assembly of BGAs on printed circuit boards through surface mount technology has encountered unprecedented challenges from thermal warpage. The excessive warpage of BGAs in the reflow process may cause manufacture problems and even the risk of failure. Thus, it is essential to acquire warpage values and corresponding distribution ranges of BGAs before the surface mount technology process. In order to avoid assembly failure, theoretically, it is necessary to guarantee that all BGA devices meet the acceptance requirement of relevant standards. Generally, a large number of samples should be measured to obtain a relatively reliable warpage data distribution in the reflow temperature range, which makes this test quite costly and extremely time consuming. This study proposes another method to estimate the BGA warpage value and its possible corresponding range from the material property point of view. Because the mechanism of BGA warpage is related to the coefficient of thermal expansion (CTE) mismatch between the different materials, the warpage data scattering can be correlated with the scattering of material properties through finite element method (FEM) analysis. With a known mean value and range of material properties, the warpage value and corresponding distribution range can be solved. A sensitivity study is also presented in this paper. The accuracy of the proposed method is evaluated and the corresponding warpage data fluctuation range is estimated. From the comparison of the simulation and experiment results, determining the material properties could lead to a reasonable prediction of warpage in both the qualitative and quantitative sense. The proposed methodology for BGA warpage estimation can be used for academic research and industrial applications.

The Integration of Taguchi Method and FAHP Method to Improve the SMT Solder Paste Printing Thickness Processing Capability

In response to the trend of miniaturization of electronic components, SMT (Surface Mount Technology) technology is become increasingly important. According to statistics, more than 70% of SMT defects occur in the solder paste printing process; hence, provided the solder paste printing process is completed correctly, the SMT yield can be maintained at a certain level. The solder paste printing process is the core of SMT technology; inability to control the process parameters may easily lead to poor solder results, which reduce product quality and increases production costs. By integrating the Taguchi and FAHP (Fuzzy Analytic Hierarchy Process) methods, this study attempted to obtain the solder thickness Cpk optimal parameters and apply DOE (Design of Experiments) in experimentation to determine the optimum SMT solder thickness parameter combination for process engineers to rapidly implement and control the SMT solder thickness process according to the optimal SMT process parameters. The empirical results suggested that, the SMT solder printing thickness processing capability Cpk value has been improved from 0.58 to 1.47, which could improve the quality of relevant electronic products.

Process Optimization for Flexible Printed Circuit Board Assembly Manufacturing

A number of surface mount technology (SMT) process variables including land design are considered for minimizing tombstone defect in flexible printed circuit assembly in high volume manufacturing. As SMT chip components have been reduced over the past years with their weights in milligrams, the torque that once helped self-centering of chips, gears to tombstone defects. In this paper, we have investigated the correlation of the assembly process variables with respect to the tombstone defect by employing statistically designed experiment. After the statistical analysis is performed, we have setup hypotheses for the root causes of tombstone defect and derived main effects and interactions of the process parameters affecting the hypothesis. Based on the designed experiments, statistical analysis was performed to investigate significant process variable for the purpose of process control in flexible printed circuit manufacturing area. Finally, we provide beneficial suggestions for find-pitch PCB design, screen printing process, chip-mounting process, and reflow process to minimize the tombstone defects.

Combining business process and failure modelling to increase yield in electronics manufacturing

The prediction and capturing of defects in low-volume assembly of electronics is a technical challenge that is a prerequisite for design for manufacturing (DfM) and business process improvement (BPI) to increase first-time yields and reduce production costs. Failures at the component-level (component defects) and system-level (such as defects in design and manufacturing) have not been incorporated in combined prediction models. BPI efforts should have predictive capability while supporting flexible production and changes in business models. This research was aimed at the integration of enterprise modelling (EM) and failure models (FM) to support business decision making by predicting system-level defects. An enhanced business modelling approach which provides a set of accessible failure models at a given business process level is presented in this article. This model-driven approach allows the evaluation of product and process performance and hence feedback to design and manufacturing activities hence improving first-time yield and product quality. A case in low-volume, high-complexity electronics assembly industry shows how the approach leverages standard modelling techniques and facilitates the understanding of the causes of poor manufacturing performance using a set of surface mount technology (SMT) process failure models. A prototype application tool was developed and tested in a collaborator site to evaluate the integration of business process models with the execution entities, such as software tools, business database, and simulation engines. The proposed concept was tested for the defect data collection and prediction in the described case study.

Sn-3Ag-0.5Cu Solder에 대한 무전해 Ni-P층의 P함량에 따른 특성 연구

ENIG (electroless Ni immersion gold) is one of surface finishing which has been most widely used in fine pitch SMT (surface mount technology) and BGA (ball grid array) packaging process. The reliability for package bondability is mainly affected by interfacial reaction between solder and surface finishing. Since the behavior of IMC (intermetallic compound), or the interfacial reaction between Ni and solder, affects to some product reliabilities such as solderability and bondability, understanding behavior of IMC should be important issue. Thus, we studied the properties of ENIG with P contents (9 wt% and 13 wt%), where the P contents is one of main factors in formation of IMC layer. The effect of P content was discussed using the results obtained from FE-SEM(field-emission scanning electron microscope), EPMA(electron probe micro analyzer), EDS(energy dispersive spectroscopy) and Dual-FIB(focused ion beam). Especially, we observed needle type irregular IMC layer with decreasing Ni contents under high P contents (13 wt%). Also, we found how IMC layer affects to bondability with forming continuous Kirkendall voids and thick P-rich layer.

Thermomechanically loaded lead-free LGA joints in LTCC/PWB assemblies

Purpose The purpose of this paper is to investigate the feasibility of using land grid array (LGA) solder joints as a second-level interconnection option in low-temperature co-fired ceramic (LTCC)/printed wiring board (PWB) assemblies for telecommunication applications. The characteristic behaviour of two commercial lead-free solder materials (Sn4Ag0.5Cu and Sn3Ag0.5Cu0.5In0.05Ni) in reflow processes and thermal cycling tests are also evaluated. Design/methodology/approach The effect of the reflow temperature profile on voiding in two lead-free solders in LTCC/PWB assemblies was investigated using X-ray and scanning electron microscopy (SEM) investigations. The test assemblies were fabricated and exposed to a temperature cycling test (TCT) in a 0-100°C or −40 to 125°C temperature range. Organic PWB material with a low coefficient of thermal expansion (CTE) was primarily used. In addition, to compare LGA assemblies with low and high global thermal mismatches, an LTCC module/FR-4 assembly was also fabricated and exposed to a TCT in a 0-100°C temperature range. The characteristic lifetime of the test assemblies was determined using DC resistance measurements. The failure mechanisms of the interconnections were verified using scanning acoustic microscopy, SEM and finite element (FE)-SEM investigations. Findings This work showed that the solderability of AgPt-metallized LTCC modules was poor, resulting in excessive voiding. This problem was avoided by using pre-tinned modules. In the test assemblies, the Sn4Ag0.5Cu joints had a lower void content and a higher characteristic lifetime compared with the Sn3Ag0.5Cu0.5In0.05Ni joints. Furthermore, it was observed that the Sn3Ag0.5Cu0.5In0.05Ni joints were more prone to fail along the interface between the Ag3Sn layer and the solder matrix than were the Sn4Ag0.5Cu joints. It was assumed that the observed difference in the primary failure mechanisms resulted in the decreased lifetime duration of the SnAgCu-InNi/Arlon in both temperature cycling conditions. Originality/value The results proved that the solderability of both solders in AgPt-metallized modules in a typical surface mount technology process was poor; however, the solderability of the test modules can be notably enhanced with pre-tinned pads. This work also demonstrated the effect of the metallization/solder pair on the failure mechanisms and failure rate in LTCC/PWB assemblies with LGA joints; the work also proved in the TCT, over a temperature range of 0-100°C, that using the present LGA joints in LTCC/PWB assemblies with a high global thermal mismatch did not increase the lifetime duration of the joints to the preferred level (3,000 cycles), whereas the performance of these joints was adequate in assemblies with a low global thermal mismatch. Moreover, the results indicated that using the LGA joint configuration enhanced the reliability of the LTCC/PWB assemblies compared with similar assemblies with collapsible ball grid array solder spheres.

Optimizing SMT Performance Using Comparisons of Efficiency Between Different Systems Technique in DEA

Surface-mount-technology (SMT) enables production of reliable printed circuit board at a reduced weight, volume, and cost. Nevertheless, SMT defects increase quality costs and deteriorate performance. In reality, defects are not equally important and their corresponding quality costs vary. In these regards, this research divides SMT defects into three classes; minor, major, and serious. Eight key factors from SMT processes are investigated concurrently with L18(21 times 37) array. Taguchi's accumulation analysis method is first applied and it provides incomplete optimal levels for some factor. In this research, each experiment is treated as a decision making unit (DMU) with defect counts set as inputs. Comparisons of efficiency between different systems (CEBDS) technique in data envelopment analysis (DEA) is then adopted to optimized SMT performance. The corresponding actual improvements in minor, major, and serious defect counts are found 0.352, 2.153, and 4.154 dB, respectively. Analysis of variance (ANOVA) is finally performed to determine significant factor effects. It is found that conveyor speed and reflow temperature are the most influential factors on SMT performance. In conclusion, the CEBDS technique turns out to be an efficient approach for optimizing process performance with categorical data.

X-ray imaging in pin-in-paste technology

Today, pin-in-paste technology is used extensively. With the help of pin-in-paste, through-hole devices can be soldered using a standard surface mount technology (SMT) process and hereby a reduction in wave soldering is possible. This can result in cost savings and a decrease in production cycle time. To ensure successful pin-in-paste soldering the following steps must be taken: solder paste volume calculations for through-hole components; stencil aperture design for the pin-in-paste application; solder paste deposition through stencil printing, application of solder volume increasing techniques after printing; reflow profile optimization; inspections using special methods for each individual process; final tests. The paste is printed into the through-holes. For high quality pin-in-paste solder joints a sufficient volume of paste is a fundamental requirement. Nevertheless, after printing the through-hole-filling is usually unknown. In this paper a new method is described how to accurately determine the volume of solder alloy in solder paste that is present in the through-hole, using X-ray measurements, image processing and calculations. In addition, a method is suggested to determine the measuring characteristics and gray-scale linearity of the X-ray machine.

Flip Chip on Board: Assessment of Reliability in Cellular Phone Application

Flip chips are generally seen as a potential future "packaging" option providing an alternative to chip scale packages. In this work, the reliability of flip chip assemblies was analyzed using daisy chain test components on a schematic test vehicle designed to emulate a cellular phone environment printed wiring board (PWB). The flip chip components were assembled in a standard surface mount technology process, where the flip chip bumps were first dipped in a flux film. A test matrix consisting of a number of flip chip test components with different input/output configurations, PWBs, fluxes, and underfills was built up. The assemblies were tested for potential damage to the flip chips and their interconnects by thermal cycling and by mechanical shock in a drop. After testing, the root causes of the failures were analyzed. As a separate task, the stress/strain generation that occurs in the flip chips in the drop test was analyzed using simulation, in order to find the critical locations on the test PWB.

Production planning for surface mount technology lines

A mathematical programming model is reported that can be used to support a key decision associated with production planning and control of surface mount technology production lines in certain environments. After a brief introduction on the nature of surface mount technology products and processes, a hierarchical view of surface mount technology production planning and control is presented, which in turn is used to organize a brief review of other published work on surface mount technology optimization. Following this, a mathematical programming model to support the making of decisions at one of the levels in the hierarchy, that concerned with allocating production lots to surface mount technology lines, is described in detail. Example results from using the model are given as well as conclusions about its value and future extensions.

SMT-compatible large-tolerance "OptoBump" interface for interchip optical interconnections

A new optical interface called OptoBump has been developed to couple optoelectronic packages to an optoelectronic printed circuit board, thus enabling economical chip-to-chip optical interconnections. The optoelectronic packages have vertical-cavity surface-emitting laser (VCSEL) and PD-array chips in their cavity and an large scale integrated (LSI) mounted on top. A package converts high-speed electrical signals from the LSI into an array of optical signals, which are emitted from the bottom. The PCB contains integrated polymer optical waveguides to optically connect packages, and the use of surface-mount technology (SMT) to mount packages on the printed circuit board (PCB) keeps assembly costs low. The key to making the OptoBump interface fully compatible with SMT is the integration of microlens arrays directly into both packages and the PCB. A wide, collimated optical beam couples a package to the board across a narrow air gap and provides a large tolerance to misalignment during the SMT process. This paper explains the concept of the OptoBump interface, the optical coupling design by ray-trace simulation, and the fabrication of polymer microlenses and polymer waveguides. Experimental results revealed that the OptoBump interface provides a large tolerance of /spl plusmn/50 /spl mu/m, which is large enough for use with SMT. The OptoBump interface can replace high-speed electrical wiring at the chip level and also offers the benefit of not having any optical fibers or connectors on the board. Thus, it has the potential to bring about a revolutionary change in optoelectronic packaging.

Fully SMT-compatible optical-I/O package with microlens array interface

A new optoelectronic package for interchip optical interconnections is presented. To make cost-effective IC-packaging and printed circuit board (PCB) assembly, we strongly emphasize the need for full compatibility with surface-mount technology (SMT). Based on the "OptoBump" interface, which couples the package and PCB by means of an array of wide, collimated beams, we developed two prototype packages: a transmitter package that contains a vertical-cavity surface-emitting laser (VCSEL) array and a driver-IC, and a receiver package that contains a photodiode (PD) array and a receiver-IC. A microlens array is integrated with each package to counteract misalignments that occur in the SMT process. All three output signals, which are E/O (O/E)-converted in the each package, exhibit clear eye diagrams at 1.25 Gb/s after the packages are surface-mounted on a PCB. The influence of polymer encapsulation on a VCSEL and an evaluation of the optical interface provided by the three optical beams on a 500-μm center-to-center spacing are also discussed.

Using statistically designed experiments for process development and improvement: an application in electronics manufacturing

The last 20 years have seen important advances on statistical experimental design. These advances have been both in methodology and in the scope of applications. Of particular interest is the application of designed experiments for process and product design, development and improvement. We present a three-phase methodology for process development and improvement based on statistically designed experiments, along with a comprehensive example for a surface mount technology process in the electronics industry.

Rheological characterization of solder pastes for surface mount applications

Accurate rheological measurements are needed in order to correlate the rheological behavior of solder pastes to their performance in the surface mount technology (SMT) process. In this paper, we summarize our efforts to measure the rheological properties of solder pastes, and outline the difficulties in obtaining their true rheological properties. In particular, we show that the rheological measurements of solder pastes are affected by "slip" at the test-apparatus surfaces and by shear fracture within the sample which have not been taken into consideration heretofore.

296 lead fine pitch (0.4 mm) thin plastic QFP package with TAB interconnect

The quad flat pack (QFP) package has become the surface mount technology (SMT) package of choice for microprocessors and peripheral devices and is well suited for hand held computer application. To address this market segment Intel has developed a new package with a thin (2.0 mm) body for light weight, low standoff (0.25 mm maximum) for overall lower profile, in a 32 mm/spl times/32 mm body format. Tape automated bonding (TAB) interconnect from die to the leadframe is used to overcome wirebond interconnect limitations. This package provides a more manufacturable package system by using flat handling during test operation. The package is trimmed and formed subsequent to test operation and shipped in standard JEDEC thin matrix plastic trays, ready to use for SMT operation with good lead coplanarity. Package reliability is equivalent to other plastic packages. Sample packages were supplied to selected customers to help develop the 0.4 mm pin pitch SMT process, equipment and materials. The feedback/results indicate that the current base of installed SMT equipment is capable of assembling such 0.4-mm pitch packages with very little or no modification and at acceptable quality levels.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>