Surface Mount Assembly Process Research Articles

An experimental study of carbonyl powder power inductor cracking during reflow process

PurposeIn surface mount assembly (SMA) process, small components are subjected to high temperature variations, which result in components’ deformation and cracking. Because of this phenomenon, cracks are formed in the body of carbonyl powder ceramic inductor (CPCI) in the preheat and cooling stages of the reflow oven. These cracks become the main cause of board failure in the ageing process. The purpose of this paper is to ascertain the thermal stress, thermal expansion of carbonyl iron ceramics and its effects on crack commencement and proliferation in the preheat stage of reflow oven. Moreover, this paper also categorized and suggested important parameters of reflow profile that could be used to eliminate these thermal shock failures.Design/methodology/approachIn this paper, two different reflow profiles were studied that evaluate the thermal shock of CPCI during varying ΔT at the preheat zone of the reflow oven. In the first profile, the change in temperature ΔT at preheat zone was set to 3.26°C/s, which has resulted in a number of device failures because of migration of micro cracks through the CPCI. In the second profile, this ΔT at preheat stage is minimized to 2.06°C/s that eliminated the thermal stresses; hence, the failure rates were significantly reduced.FindingsTMPC0618H series lead (Pb)-free CPCI is selected for this study and its thermal expansion and thermal shock are observed in the reflow process. It is inferred from the results that high ΔT at preheat zone generates cracks in the carbonyl powder-type ceramics that cause device failure in the board ageing process. Comparing materials, carbonyl powder ceramic components are less resistant to thermal shock and a lower rate of temperature change is desirable.Originality/valueThe proposed study presents an experimental analysis for mitigating the thermal shock defects. The realization of the proposed approach is validated with experimental data from the printed circuit boards manufacturing process.

The Impact of Stencil Printing Upon Assembly & Reliability Of 0.3mm Pitch CSP Components

Abstract With the continual shrinking of electronic assembly form factors, designers are being forced towards smaller, more complex components with decreasing interconnection pitches. As a consequence, the Surface Mount assembly process is becoming increasingly challenged. For the stencil printing process, this means that historically accepted stencil aperture area ratio design rules, (which dictate what can or cannot be printed), need to be significantly pushed to extend the printing process for next generation ultra -fine pitch components. As a result, a major study has been undertaken looking at several different aspects of the stencil printing process, and their impact upon the assembly and reliability of 0.3mm pitch CSP components. In a preliminary test, stencil printing factors such as stencil aperture size and printing technology (standard squeegees vs ultrasonically aided active squeegees) were investigated. Data showed that the active squeegees provided a significantly larger process window. Subsequently, components were assembled using a range of solder paste volumes printed with both standard and active squeegee technology. The components assembled using an active squeegee process exhibited higher assembly yield, and also extended reliability when subjected to thermal cycling.

Development of a High Temperature Interconnect Solution as an Alternative to High Lead or Gold Content Solders

AbstractA collaborative research programme between project partners Microsemi, the National Physical Laboratory (NPL) and Gwent Electronic Materials (GEM), has successfully developed innovative materials specifically designed to offer an alternative for high Pb or Au content materials to increase the operating temperature of electronic assemblies. Currently, for electronic assemblies to operate at high temperature, they must use a high lead solder or a very expensive gold based solder to withstand these temperatures. The ELCOSINT project has developed an inexpensive lead-free alternative for joining high temperature electronics suitable for operating at temperatures above 250°C utilising standard surface mount assembly processes. This paper summarises the work undertaken by the authors to develop and better understand this new family of electrical interconnection materials. The project brought together a materials supplier (GEM – Gwent Electronic Materials), an end-user (MSL - Microsemi) and an technology research organisation (NPL – National Physical Laboratory) to jointly develop, test and implement in production, the solution based on silver-loaded silicone materials. This paper focuses on the testing and materials evaluation undertaken at NPL to determine the long term performance of these alternative materials including high temperature ageing up to 300°C, thermal cycling and damp heat testing. Details of the shear strength and electrical performance of interconnects between the substrates and components during the test regimes are given. The manufacturing process is outlined including details of the test vehicles utilised. The processing temperature for the conductive adhesive is 250°C which offers additional advantages in potential improvements in component and substrate reliability compared to soldered solutions which would typically be processed at temperatures above 300°C.

Stencil Printing Process Guidelines for 0.3mm Pitch Chip Scale Packages

With the form factor of electronic assemblies continuing to shrink, designers are being forced towards smaller, more complex components with decreasing interconnection pitches. As a consequence, the Surface Mount assembly process is becoming increasingly challenged. For the stencil printing process, todays accepted stencil area ratio rules, (which dictate what can or cannot be printed), need to be significantly pushed to extend the printing process for next generation ultra -fine pitch components. With aperture geometries shrinking, anything which can influence solder paste transfer efficiency has to be considered. New process technologies such as ultrasonic squeegees have emerged in recent years to assist the process with some degree of success. However, something which is often overlooked in terms of stencil design influence is that a square shaped aperture, size for size, has a volume which is 21.5% than its circular counterpart. In a process where quite literally every solder particle that can be printed is becoming significant then this fact can be utilized to the process engineer's advantage. In this paper, the merits of stencil aperture shape, in conjunction with ultrasonic squeegees are investigated with the purpose of developing stencil printing guidelines for ultra-fine pitch components such as 0.3mm pitch CSP's.

Application of Lamination Theory to Study Warpage Across PWB and PWBA During Convective Reflow Process

Out-of-plane displacement (warpage) has been a major reliability concern for board-level electronic packaging. Printed wiring board (PWB) and component warpage results principally from coefficient of thermal expansion (CTE) mismatch among the materials that make up the PWB assembly (PWBA). Warpage occurring during surface-mount assembly processes and normal operations may lead to severe solder bump failures. In this paper, the classical laminated plate theory was applied to study the warpage behavior of PWBs and PWBAs during the thermal reflow process. The rule of mixtures was used to estimate the effective material properties of PWBA composites. Closed form solutions of the differential equations for the PWB and PWBA deformation were generated from the classical lamination theory to evaluate the sample warpage. The board support conditions and thermal gradients through the assembly thickness were considered in the theoretical model. The calculated warpage results were compared with experimental results using the projection moiré measurement system in a simulated convective reflow process to evaluate the accuracy of the model. Finite element modeling was applied to estimate the sample warpage values under the same thermal loading and boundary constraints. The warpage values obtained from the theoretical models show high sensitivity to the thermal loads, through-the-thickness temperature gradients of the test samples, and CTE values of the composite materials. The relative warpage results obtained from the theoretical models and numerical models agreed well with the experimental measurement results during the thermal reflow process.

Developments in Stencil Printing Technology for 0.3mm Pitch CSP Assembly

As electronics assemblies continue to shrink in form factor, forcing designers towards smaller components with decreasing pitches, the Surface Mount assembly process is becoming increasingly challenged. A new “active” squeegee printing process has been developed to assist in the stencil printing of solder pastes for next generation ultra fine pitch components such as 0.3mm pitch CSP’s. Results indicate that today’s accepted stencil area ratio rules, which govern solder paste transfer efficiency can be significantly pushed to extend stencil printing process capabilities to stencil apertures having area ratios as low as 0.4. Such a breakthrough will allow the printing of ultra fine pitch components and additionally will assist with heterogeneous assembly concerns, to satisfy up and coming mixed technology demands.

Reducing Solder Paste Inspection in Surface-Mount Assembly Through Mahalanobis–Taguchi Analysis

Increased functional density and reduced input/output (I/O) spacing are the market trends in the electronics manufacturing industry. Industry reports indicate that approximately 50%-70% of soldering defects are attributed to the solder paste printing process for printed circuit board (PCB) assembly. Hence, after the printing process, a solder paste inspection (SPI) system is generally used to examine the amount of solder paste deposition. Effective selection of components and bonding pads during solder inspection is extremely important in achieving desired process cycle times and ensuring assembly yield. This paper uses the Mahalanobis-Taguchi system to establish a systematic approach to determining guidelines for solder paste inspection. Among a total of 203 bonding pads on the board for a GPS product, the optimal model suggests that the solder deposition of 121 bonding pads be inspected. The reduction ratio is 40.4%, and the feasibility of the proposed model is verified. Also, for those bonding pads to be inspected for their solder paste deposition, this study uses empirical data to define the specifications to effectively distinguish acceptable PCB samples from defective. The threshold is within the 100% capability for judgment of solder paste printing quality in the surface mount assembly process.

Fatigue Assessment of Solder Bumps on Board Assemblies Affected by PWB Warpage

Out-of-plane displacement (warpage) has been a major reliability concern for board-level electronic packaging. Printed wiring board (PWB) and component warpage results from CTE mismatch among the materials that make up the PWB assembly (PWBA). Warpage occurring during surface-mount assembly processes and normal operations may lead to severe solder bump failures. In this research, the effect of PWB warpage on the low cycle fatigue of the solder bumps in plastic ball grid array (PBGA) packages was studied. Finite element modeling (FEM) was used for the strain-based life prediction of solder bumps on board assemblies. In this paper, 3-D models of PWBAs with varying board warpage were used to estimate the solder bump fatigue life for different types of PBGAs mounted on PWBs. In order to improve the accuracy of FE results, the projection moiré method was used to measure the initial warpage of PWBs, and this warpage was used as a geometric input to the FEM. The PWBAs with known PWB warpage were modeled to determine the influence of various levels of initial PWB warpage on the low cycle fatigue failure of solder bumps. The effect of different types of PBGAs with varying locations on solder bump fatigue was studied. Both Sn-Pb and lead-free solder materials were used in this study. The FE models were validated with experimental results obtained using the projection moiré technique. The FE results showed that the initial PWB warpage has significant a effect on the fatigue reliability of solder bumps in PBGA packages.

Parametric study of warpage in printed wiring board assemblies

Out-of-plane displacement (warpage) causes mis-registration, delamination, possibly solder joint opening(s), and other printed wiring board assembly (PWBA) failures during surface-mount assembly processes and life-span operations. Many material, geometry, and process related parameters contribute to the warpage of a PWBA. The objective of this paper is to investigate these parametric effects on PWBA warpage. Based on the parametric study, the identified material, geometry, and process parameters can then be optimized to achieve the most reliable product. In this paper, a PWBA test vehicle consisting of a four-layer PWB and a surface-mount ball grid array package is studied. Its warpage during infrared reflow is measured by the shadow moire/spl acute/ method to validate finite-element results. The validated modeling results are used for parametric study. In the parametric study, Taguchi and full-factorial design of experiments (DOE) are adopted to systematically vary parameters that are of interest. After running experiments based on DOE, analysis of variance is employed to identify the influential parameters. Thereafter, the warpage data is regressed with respect to the identified influential parameters. According to the regression model, the influential parameters can be optimized within practical range to achieve the least warped design.

Application of numerical analysis to the optimisation of electronic component reliability screening and assembly processes

This study investigates the prediction of transient board-mounted electronic component heat transfer in environments representative of reliability screening and surface-mount assembly processes using computational fluid dynamics (CFD) analysis. The test cases are based on a board-mounted 160-lead Plastic Quad Flat Pack (PQFP) component, analysed in still-air and a range of forced airflows. For reliability screening, three types of transient operating conditions are considered, namely (i) component dynamic power dissipation in fixed ambient conditions, (ii) passive component operation in dynamic ambient conditions, and (iii) combined component dynamic power dissipation in varying ambient conditions. For surface-mount assembly, the test vehicle is exposed to a typical solder reflow thermal profile. Benchmark criteria are based on component junction temperature and component-printed circuit board (PCB) surface temperature, measured using thermal test dies and infrared thermography, respectively. Component/PCB numerical modelling is based on nominal geometry dimensions and material properties. Overall, component transient thermal behaviour is found to be accurately predicted, suggesting that CFD analysis could play an important role in providing critical boundary conditions to determine accelerated life testing parameters and optimise new assembly processes.

Issues that impact the conversion to a no-clean surface mount assembly process

The surface mount assembly industry, especially the contract manufacturing segment, is currently undergoing a transition from an assembly process that requires a cleaning step to one that does not. In addition, maximization of yields is critical to the contract assembly environment. This paper addresses both these issues. Factors that impact the conversion to a no-clean process are discussed along with those that impact first pass yields. A systematic process that can be implemented to maximize yields is provided.

Development of the surface mount assembly process through an angular board orientation

This paper proposes a methodology to improve the process time required for the component placement process of the printed circuit board assembly with an X-Y positioning table. The methodology is applied to a previously published subproblem as well as a real-life working board configuration. Even with high speed assembly machines placing in excess of 40000 components per hour (cph), process improvements are possible. Concentrating on the path planning portion is a valid method to increase efficiency, but as the problem approaches optimality, the planning process essentially becomes counterproductive due to the time and effort required. This paper presents an algorithm for system time improvement for use after a board placement path is established. In order to take advantage of the machine's capability to move the positioning table along each axis simultaneously, the board is physically rotated with respect to the positioning table. This paper steps through the theoretical development of a method to determine the proper angle of rotation, first for a regular 'rectangular' board configuration, and then for a more applicable 'general' configuration.

A practical lifetime prediction method for inter-poly oxides : Andreas Martin, Paula O'Sullivan and Alan Mathewson. Electron Technology, 27, 1, 55 (Warsaw 1994)

This study investigates the prediction of transient board-mounted electronic component heat transfer in environments representative of reliability screening and surface-mount assembly processes using computational fluid dynamics (CFD) analysis. The test cases are based on a board-mounted 160-lead Plastic Quad Flat Pack (PQFP) component, analysed in still-air and a range of forced airflows. For reliability screening, three types of transient operating conditions are considered, namely (i) component dynamic power dissipation in fixed ambient conditions, (ii) passive component operation in dynamic ambient conditions, and (iii) combined component dynamic power dissipation in varying ambient conditions. For surface-mount assembly, the test vehicle is exposed to a typical solder reflow thermal profile. Benchmark criteria are based on component junction temperature and component-printed circuit board (PCB) surface temperature, measured using thermal test dies and infrared thermography, respectively. Component/PCB numerical modelling is based on nominal geometry dimensions and material properties. Overall, component transient thermal behaviour is found to be accurately predicted, suggesting that CFD analysis could play an important role in providing critical boundary conditions to determine accelerated life testing parameters and optimise new assembly processes.

Application of Statistical Clustering to Screen Printing Process Control

Statistical clustering is applied for mathematical description of a surface mount assembly process. The clustering model, intended for process control applications, defines the correspondence between various outcomes of the process and particular regions in the space of process variables. An adaptive version of the clustering model is presented. Prediction, regime selection and control procedures, utilizing the clustering model, are formulated.

Flip Chip Rework Process

This paper discusses chip removal and replacement processes of flip chip assemblies (FCAs) on printed wiring boards (PWBs). The original chip connection is achieved via mass reflow as in a surface mount assembly process. The FCA interconnection is one involving a surrogate solder bump on a chip and a lower melt solder on the PWB pads that fuses with the bump during reflow. The chip removal process thus entails melting the lower melt solder locally using hot gas. The following considerations will be discussed in the paper: chip size, chip removal methodology, local vs mass reflow for replacement attachment, solder height, the impact of multiple reflows on the solder joint integrity of assemblies. The use of the flip chip rework machine to remove ball grid arrays (BGAs) and quad flatpacks (QFPs) will be briefly addressed.

Application of Impedance Spectroscopy for On-Line Monitoring of Solder Paste

The technique of impedance spectroscopy is suggested for industrial monitoring of solder paste in the surface mount assembly process. Being an on-line implementable technique, it has the potential of giving valuable insight to the manufacturing characteristics of solder paste and can facilitate application of statistical process control methods. This exploratory study evaluates impedance spectroscopy as a monitoring tool and focuses on key topics which can lead to the creation of on-line standards for solder paste. The presented technique is supported by experimental results and statistical analysis.

Predicting Scooping and Skipping in Solder Paste Printing for Reflow Soldering of SMT Devices

This paper examines the rôle that the squeegee plays in the solder paste printing process. Although the printing of solder paste is only one stage of many in the surface mount assembly process, it is crucial to deposit the correct amounts of solder paste cleanly onto the substrate. The amount of solder paste deposited affects the reliability and strength of the reflowed solder joint. Surface mount component lead pitches are continually being reduced due to the requirements of packing more and more components into a given space on the PCB, and this necessitates a proper understanding of the printing process and in particular of the squeegee which plays an important part in determining paste heights and the occurrence of defects. The paper outlines a model which predicts scooping and skipping in the stencil printing of solder pastes used in the reflow soldering of surface mounted devices. The model is based on the forces acting on the squeegee blade, which determines the paste flow pattern ahead of the squeegee, and on the stencil aperture geometry. The paper also examines the interactions between the paste properties and squeegee material properties. These interactions produce printing defects such as scooping, skipping and wet bridging. Results of an experimental comparison of different types of squeegee blade used in the stencil printing of solder pastes for reflow soldering in SMT, as well as the experimental results for squeegee deformation into stencil apertures, were used for validating the model. The empirically enhanced model which results takes into account the force on the squeegee due to solder paste flow and some of the non‐Newtonian properties of the solder paste. The main utility of the proposed model is the control of solder paste printing quality.