Suppression Of Unwanted Harmonics Research Articles

A Low Noise D-Band VCO With a Wide Bandwidth and a Steady Output Power

A 129–159 GHz frequency synthesizer is implemented using a low phase noise (PN) 43–53 GHz VCO core driving a featured tunable differential tripler. The load of the proposed tripler can be tuned to the third harmonic of the input frequency to adaptively maximize the output power over the entire range of output bandwidth. The fabricated chip achieves maximum output power of ${-}8$ dBm, and the average PN for the VCO core is ${-}99.6$ dBc/Hz and ${-}115.5$ dBc/Hz at 1 MHz and 10 MHz offsets, respectively. Having the frequency tuning range of almost 30 GHz, this is the widest-band width, 65 nm D-band CMOS signal source reported to this date which can precisely sustain the high output power at its wide output bandwidth. The synthesizer consumes 95 mW of power, which corresponds to an average FOM of ${-}173$ dBc/Hz. Suppression of unwanted harmonics is better than 31 dBc across the entire bandwidth. The core design occupies only 300 $\,\times\,$ 250 $\mu$ m.

X-Band to W-Band Frequency Multiplier in 65 nm CMOS Process

A compact single chip x9 frequency multiplier from X band to W band implemented in 65 nm CMOS is presented. A chain of five transformer coupled stages is used, including two triplers, realized with differential common source amplifiers at class-C mode. The circuit reaches saturated output power of -3.2 dBm at 91.8 GHz with a 7.2% bandwidth from 88.9 to 95.5 GHz. The suppression of unwanted harmonics is better than 16 dBc across the bandwidth. The core design occupies 246 μm × 706 μm and consumes 120 mW from a 1.2 V supply. Supply voltage increase to 1.3 V yields a peak output power of -2.7 dBm and 160 mW of dc power.

A W-Band $\times$12 Multiplier MMIC With Excellent Spurious Suppression

This letter presents a single chip × 12 frequency multiplier MMIC for the W-band that is realized in a 100 nm metamorphic HEMT technology. To obtain the × 12 multiplication factor a multiplier chain of a doubler, a tripler and a doubler has been cascaded. The circuit has a 3 dB bandwidth of 15 GHz from 85 to 100 GHz. At 94 GHz, the multiplier achieves a saturated output power of more than 1 dBm and a conversion gain of 0 dB. The suppression of unwanted harmonics is better than 30 dBc at 94 GHz and better than 24 dBc within the entire bandwidth.

Suppression of Unwanted Harmonics Using Integrated Complementary Split-Ring Resonators in Nonlinear Transmission Line Frequency Multipliers

Inspired by the distributed nature of nonlinear transmission lines (NLTLs), a novel filtering method that integrates the filter stages within the NLTL periodic structure is introduced to suppress unwanted signals. To implement the filter, compact complementary split-ring resonators are designed and included in a coplanar waveguide-based NLTL frequency doubler. Analytical derivations for the filter design and prediction of the dispersion characteristics are presented. Measurement results are reported to validate the efficiency of the method demonstrating improvement in third harmonic suppression and reduced sensitivity to the variation of the input voltage level.

Frequency multiplier using waveguide-based spatial power-combining architecture

In this paper, an architecture of a frequency multiplier is proposed and demonstrated with emphasis on the development of a 12-24-GHz frequency doubler based on a waveguide spatial power-combining technique. This frequency doubler is designed by spatially combining four monolithic-microwave integrated-circuit multiplier chips operating from 11-13 to 22-26 GHz. The output power obtained is 22.6 dBm for 21-dBm input power, which corresponds to a combining efficiency of 74%. The suppression of unwanted harmonics has been achieved by inherent properties of the architecture. The suppression of the first harmonic obtained in this paper is more than 65 dB, whereas at least 25 dB is expected for the third harmonic. This new design technique optimizes the conversion efficiency and also allows a significant loss reduction, as the usually needed output filters are no longer required.

An upper sideband upconverter using MIS varactors

The basic properties of the metal insulator semiconductor (MIS) varactor are explained. Its application in an upper sideband upconvertor at an RF of 2.3 GHz and an IF of 70 MHz is investigated and compared to that of a charge storage varactor. It is shown that the MIS varactor is in many respects superior to the charge-storage varactor in tuning, optimization of RF efficiency, stability, suppression of unwanted harmonics, and bandwidth.

Carrier-frequency generation using regular pulse sequences

The formation of simple pulse sequences, by the periodic gating of pulse trains, is considered as a method for generating sets of harmonically related frequencies at increased levels and with some suppression of unwanted harmonics. The method may be used to generate the carrier frequencies for multichannel transmission systems.