Abstract
A 129–159 GHz frequency synthesizer is implemented using a low phase noise (PN) 43–53 GHz VCO core driving a featured tunable differential tripler. The load of the proposed tripler can be tuned to the third harmonic of the input frequency to adaptively maximize the output power over the entire range of output bandwidth. The fabricated chip achieves maximum output power of ${-}8$ dBm, and the average PN for the VCO core is ${-}99.6$ dBc/Hz and ${-}115.5$ dBc/Hz at 1 MHz and 10 MHz offsets, respectively. Having the frequency tuning range of almost 30 GHz, this is the widest-band width, 65 nm D-band CMOS signal source reported to this date which can precisely sustain the high output power at its wide output bandwidth. The synthesizer consumes 95 mW of power, which corresponds to an average FOM of ${-}173$ dBc/Hz. Suppression of unwanted harmonics is better than 31 dBc across the entire bandwidth. The core design occupies only 300 $\,\times\,$ 250 $\mu$ m.
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