Supply Voltage Research Articles

An ultra energy-efficient hardware platform for neuromorphic computing enabled by 2D-TMD tunnel-FETs

Brain-like energy-efficient computing has remained elusive for neuromorphic (NM) circuits and hardware platform implementations despite decades of research. In this work we reveal the opportunity to significantly improve the energy efficiency of digital neuromorphic hardware by introducing NM circuits employing two-dimensional (2D) transition metal dichalcogenide (TMD) layered channel material-based tunnel-field-effect transistors (TFETs). Our novel leaky-integrate-fire (LIF) based digital NM circuit along with its Hebbian learning circuitry operates at a wide range of supply voltages, frequencies, and activity factors, enabling two orders of magnitude higher energy-efficient computing that is difficult to achieve with conventional material and/or device platforms, specifically the silicon-based 7 nm low-standby-power FinFET technology. Our innovative 2D-TFET based NM circuit paves the way toward brain-like energy-efficient computing that can unleash major transformations in future AI and data analytics platforms.

An analytical design and analysis of a high gain switched inductor voltage multiplier cell power converter

The proposed modified higher gain boost converter employs switched Inductor and multiplier cell-based voltage boosting techniques, as the paper represents. This converter is modelled to enhance the static gain and efficiency. As the designed topology has an incessant source current at its input side, it is ideal for solar PV applications. With a power capacity of 100 W, the proposed topology is designed to work on 24 V source input and 200 V load/output voltage. The load voltage is maintained by a PI controller, which achieves the highest efficiency of 92% under rated load conditions. The converter’s transient performance with the controller is investigated under various situations, including supply voltage variation, reference voltage variation, and load power variation. Finally, the designed converter’s experimental model is created to evaluate the simulated and conceptual results.

A 0.73 mW low power 9.6 GHz LC voltage-controlled oscillator achieves constant KVCO and −189.2 FOM

This article introduces a novel approach of LC voltage-controlled oscillator (VCO) to overcome the challenges present in the Phase-locked loop (PLL) in high-frequency applications and proposes a 9.6 GHz VCO based on gm-boosted structure. By utilizing a transformer and gain variation calibration technique, the proposed VCO reduces the losses caused by MOSFET’s operation in triode region, thereby improving phase noise. And KVCO remains relatively constant, fluctuating up and down by approximately 5 MHz around 100 MHz/V, which is suitable to be used in phase-locked-loops (PLL). The oscillator is fabricated in 22 nm CMOS process occupying 0.25 mm × 0.55 mm area and consuming 0.73 mW from 0.5 V supply voltage. The measured phase noise achieves −114.3 dBc/Hz at 1 MHz offset with a carrier frequency of 4.75 GHz, and the figure of merit (FoM) is −189.2 dBc/Hz. The results clearly demonstrate that the proposed design could work under low power consumption and achieve constant KVCO, making it well suitable for high-frequency PLL applications.

A Method to Correct the Temporal Drift of Single-Photon Detectors Based on Asynchronous Quantum Ghost Imaging.

Single-photon detection and timing has attracted increasing interest in recent years due to their necessity in the field of quantum sensing and the advantages of single-quanta detection in the field of low-level light imaging. While simple bucket detectors are mature enough for commercial applications, more complex imaging detectors are still a field of research comprising mostly prototype-level detectors. A major problem in these detectors is the implementation of in-pixel timing circuitry, especially for two-dimensional imagers. One of the most promising approaches is the use of voltage-controlled ring resonators in every pixel. Each of these runs independently based on a voltage supplied by a global reference. However, this yields the problem that the supply voltage can change across the chip which, in turn, changes the period of the ring resonator. Due to additional parasitic effects, this problem can worsen with increasing measurement time, leading to drift in the timing information. We present here a method to identify and correct such temporal drifts in single-photon detectors based on asynchronous quantum ghost imaging. We also show the effect of this correction on recent quantum ghost imaging (QGI) measurement from our group.

J-MISFET Hybrid Dual-Gate Switching Device for Multifunctional Optoelectronic Logic Gate Applications.

High-performance and low operating voltage are becoming increasingly significant device parameters to meet the needs of future integrated circuit (IC) processors and ensure their energy-efficient use in upcoming mobile devices. In this study, we suggest a hybrid dual-gate switching device consisting of the vertically stacked junction and metal-insulator-semiconductor (MIS) gate structure, named J-MISFET. It shows excellent device performances of low operating voltage (<0.5 V), drain current ON/OFF ratio (∼4.7 × 105), negligible hysteresis window (<0.5 mV), and near-ideal subthreshold slope (SS) (60 mV/dec), making it suitable for low-power switching operation. Furthermore, we investigated the switchable NAND/NOR logic gate operations and the photoresponse characteristics of the J-MISFET under the small supply voltage (0.5 V). To advance the applications further, we successfully demonstrated an integrated optoelectronic security logic system comprising 2-electric inputs (for encrypted data) and 1-photonic input signal (for password key) as a hardware security device for data protection. Thus, we believe that our J-MISFET, with its heterogeneous hybrid gate structures, will illuminate the path toward future device configurations for next-generation low-power electronics and multifunctional security logic systems in a data-driven society.

Design of improved write and read performance 12T sram cell with leakage power control technique

Currently, memory occupies nearly eighty-five percent of the allocated chip area. Integrated electronics, such as workstations and mobile gadgets, need quick memory systems that use low power. Scaling issues make it impossible to obtain low-power and resilient SRAM cells, which are critical for Internet of Things (IoT) devices, using CMOS semiconductor technology. New nanoscale technologies, like FinFET, are being proposed as a substitute for CMOS in SRAM architecture. The study introduces a novel 12T SRAM cell design using FinFET technology, including differential writing and single-ended reading operation facilitated by write-read circuitry. The cell employs a write-assist-based approach to enhance the stability of reading and writing operations accordingly. In addition to differential writing architectures, single-ended reading decreases power use, while stacking transistors and minimizing read bit-line leakage minimizes leakage power utilization. The cell's performance has been evaluated utilizing a Cadence Spectre simulator featuring 18-nm FinFET technology and compared to current SRAM architectures at a supply voltage of 0.8 V. PVT variations are conducted to evaluate the efficiency of the suggested SRAM design. The reading and writing stability of the new SRAM cells has been enhanced by a minimum of 10 % when compared with the current counterparts. A 15 % decrease in power consumption has been seen in the suggested design compared to conventional SRAM cells of the same technology.

Inductor-Less Broadband Energy-Efficient Active Balun up to 60GHz

The paper presents a non-inductive broadband energy-efficient active balun based on a differential pair, intended for use in the input block of a frequency divider for 22nm technology. The developed device can operate in the frequency range from 2 GHz to 60 GHz with a supply voltage of 0.8 V and consume less than 3 mA. The special feature of the developed active balun is that it does not have inductive components, which reduces its size and signal loss. Amplitude of the output signal in working frequency range is from 450 mV to 200 mV. Signal gain in the range from 1-60 GHz varies from -10 dB up to 4 dB. The size of the circuit on the chip is 48x34 um. The device allows you to receive a stable signal at high data transfer rates and provides energy savings due to low current consumption.

A concise high‐efficiency broadband parallel‐circuit Class‐E power amplifier

SummaryAn analysis of a single‐ended high‐efficiency broadband parallel‐circuit (PC) Class‐E power amplifier (PA) with a single reactance compensation technique (RCT) and low‐pass (LP) Chebyshev impedance transformer is first presented under low supply voltage. Analysis of the gate and drain voltage allows to determine the required optimum voltage values for the expected PA design objectives. Derivation and design procedure of the broadband matching network (MN) is provided, which can effectively filter out higher order harmonics and reduce circuit complexity. In addition, the load adaptability for this PA is studied, achieving higher than 67.87% drain efficiency (DE) in the case of load mismatch. A PC Class‐E PA based on NMOS transistor is designed and implemented to validate the analysis over a frequency band of 7–9.4 MHz. Experimental results show that the PA delivers 36.48–38.83 dBm output power with a DE of 84.91% to 86.91%, as well as achieves 83.98% to 86.28% power‐added efficiency (PAE), 19.48–21.83 dB gain with a low supply voltage of 12 V. It is also demonstrated that the experimental results exhibit good agreement with the simulation results, which prototype the radio frequency identification transmitter with broadband high‐efficiency and system compactness. To the author's knowledge, this study represents the first approach to design broadband PC Class‐E PA under low supply voltage for Internet of Things (IoT) applications at HF frequency band, such as electronic article surveillance (EAS) system.

Pure sine wave generation in battery-less solar system using advanced control through single machine

Due to the reduction of conventional energy sources, humanity faces a critical challenge, forcing innovative solutions to bridge the growing gap between energy demand and supply. Solar energy has emerged as a promising alternative, owing to its efficiency and renewable nature. Despite their benefits, conventional solar power systems face many challenges, including their reliance on battery banks, which introduce complexities and inefficiencies, such as voltage fluctuations and harmonic content. To overcome these challenges, researchers propose a novel solution: the Dual Winding Machine (DWM). This innovative system integrates motor and generator functionalities within a single machine, operating on a dual stator core to achieve synchronous operation. In contrast to traditional setups, the DWM eliminates the need for batteries during periods of low solar energy. A crucial component in this novel approach is the utilization of a Zeta converter, which adjusts the switching frequency to regulate the DC voltage and machine terminals. By doing so, the DWM maintains a constant voltage supply without relying on a battery, mitigating the fluctuations observed in traditional solar power systems. The proposed solution offers several benefits over existing strategies. Firstly, by eliminating the need for a battery, the DWM reduces system complexity and enhances overall efficiency. The absence of a battery backup also minimizes the risk of fluctuations in the inverter's input voltage and mitigates potential increases in output harmonic content. This not only improves the reliability of the solar power system but also extends the lifespan of connected machinery, such as motors and electrical devices. Furthermore, simulations conducted using MATLAB and MAXWELL programs validate the effectiveness of the DWM, confirming its ability to generate harmonic-free sine waves without relying on a battery, thus representing a significant advancement towards more sustainable and reliable solar energy solutions. In summary, the DWM presents a promising solution to the challenges faced by conventional solar power systems, offering improved efficiency, reliability, and longevity.

Research on the Effects of Voltage Sags and Harmonics on the Output Characteristics of Switching Power Supply

Switching power supply is widely used in industrial equipment, household appliances, and other fields due to the advantages of high integration and lightweight. Voltage sags can seriously affect the output voltage of switching power supply and the working condition of its power supply equipment; at the same time, the working scenarios of power equipment using switching power supply often have different level of harmonic problems. Considering the continuous innovation of switching power supply technology, the previous analysis and test results on the effect of voltage sags and harmonics on switching power supplies may no longer be applicable. The paper reveals the mechanism of the effect of harmonic alone as well as voltage sag superimposed harmonics on the output voltage of the switching power supply. Then the test research program was developed, and four different brands switching power supplies were selected for the test research, with which the effects of different amplitude voltage sags, harmonics with different frequencies and distortion, as well as voltage sag superimposed harmonics on the output voltage of switching power supplies were investigated. The results show that the tolerance ability of switching power supplies to voltage sags has been improved compared with previous switching power supplies, and the harmonic itself has less effect on the output voltage of switching power supply, but the joint action of harmonics and voltage sags will have a greater effect on the output voltage of switching power supply. © 2024 Institute of Electrical Engineers of Japan and Wiley Periodicals LLC.

A Ternary Inverter Based on Hybrid Conduction Mechanism of Band-to-Band Tunneling and Drift-Diffusion Process.

In this paper, a novel transistor based on a hybrid conduction mechanism of band-to-band tunneling and drift-diffusion is proposed and investigated with the aid of TCAD tools. Besides the on and off states, the proposed device presents an additional intermediate state between the on and off states. Based on the tri-state behavior of the proposed TDFET (tunneling and drift-diffusion field-effect transistor), a ternary inverter is designed and its operation principle is studied in detail. It was found that this device achieves ternary logic with only two components, and its structure is simple. In addition, the influence of the supply voltage and the key device parameters are also investigated.

A 500 mVpp Input Range First-Order VCO-Based ADC with a Multi-Phase Quantizer for EEG Recording Front Ends

This paper proposes a VCO-based ADC with first-order noise shaping for EEG signal recording front ends. Addressing the challenge of applying analog integrators in advanced processes due to low voltage issues, a multi-phase quantizer structure is introduced based on V-F conversion within the VCO structure, resulting in lower analog power consumption at the same output bit-width. By introducing a form of Gray code encoding, errors caused by circuit metastability are limited to within 1 bit. Considering the effects of motion artifacts and the electrode DC offset, the circuit achieves a wide input range of 500 mVpp by adjusting the feedback coefficients. A prototype ADC is fabricated using 180 nm CMOS technology, operating at a 1.8 V/1 V power supply voltage, with power consumption of 17.1 μW, while achieving a 62.1 dB signal-to-noise and distortion ratio (SNDR) and 55.2 dB dynamic range (DR). The proposed ADC exhibits input noise of 8.64 μVrms within a bandwidth of 0.5 Hz–5 kHz.

A Low-Power Tunable Differentiator Using Voltage Difference Transconductance Amplifier (VDTA) for Tunable PD Controller

The electronically tunable differentiator using a voltage difference transconductance amplifier (VDTA) is proposed, designed, and analyzed. The simulation was done using the Cadence Virtuoso tool of 45[Formula: see text]nm CMOS technology with a supply voltage of ±0.9[Formula: see text]V. The maximum power consumption of the proposed circuit is 246[Formula: see text][Formula: see text]W with a total harmonic distortion of 5.4%. The output can be tuned using four parameters: [Formula: see text], [Formula: see text], [Formula: see text], and [Formula: see text]. The transconductance can be varied using bias current and aspect ratio of CMOS transistors. The utilized area of VDTA layout is [Formula: see text]. The parasitic impedance affects the output of post-layout simulation and causes little delay compared to schematic. The design has been experimentally verified using LM13700 integrated circuit. The results of the proposed circuit show good agreement with the experimental results and mathematical expressions. The proposed circuit can be used as a tunable PD controller, in which the voltage gain of the proposed circuit is [Formula: see text]. The design is versatile and can be used in different applications such as temperature control systems, photo voltaic cells, waveform generators, microwave communications systems, and instrumentation systems.

Performance analysis of three-phase solar PV, BESS, and Wind integrated UPQC for power quality improvement

UPQC (Unified Power Quality Conditioner) is indeed a Versatile power conditioner which could be utilized to adjust for a variety of power supply voltage disturbances, rectify voltage fluctuation, and minimize harmonic load current in accessing the power source. To ensure a continuous power supply. We are making use of UPQC technology in combination with shunt and series AFC (Active filter compensators) to counteract power quality problems resulting from grid harmonics and nonlinear loads. Therefore, the focus of this research is to analyze the UPQC's system performance under swell and sag with the variation of solar irradiation and temperature. To achieve these two distinct cases of PV system like temperature-25 °C, irradiance-700 W/m2, and temperature-45 °C, irradiance-800 W/m2, are considered respectively. The implementation of the FOPI controller purposes to bolster power quality of 3-phase HESS (hybrid energy storage system), which includes an integrated UPQC for outstanding performance. In order to manage harmonics resulting from non-linear loads and reduce grid power quality issues, the UPQC model integrates both shunt and series AFC. In the case of extended voltage interruptions, the integrated UPQC with BESS, wind and PV can effectively resolve power quality concerns. The UPQC shunt compensator efficiently harnesses power from HES (hybrid energy systems), whereas the series compensator acts as a guardian, protecting the load from power quality issues originating in the grid. In order to regulate the voltage of the DC connection at a desired level, the aim of this article is to develop a FOPI controller with isodamping properties. In particular, a novel hybrid algorithm called the Enhanced Seagull with Rooster Update (ES-RU) Algorithm, which combines the ideas of Chicken Swarm Optimization (CSO) and Seagull Optimization algorithm (SOA), optimally tunes the gain of the FOPI controller. For optimal performance, the FOPI controller's gain parameters (Kp, Ki, λ) are finely tuned using an Enhanced Seagull with Rooster Update (ES-RU) Algorithm. As a consequence, the performance of the adopted and extant models is examined during sag and swell conditions with respect to source voltage and load voltage and compared with other conventional models like PI, FF, CS and SG, respectively for both cases like temperature-25 °C, irradiance 700 W/m2, and temperature-45°C, irradiance-800 W/m2, correspondingly. The overshot and total harmonic distortion (THD) of the proposed ES-RU is superior to the existing models like PI, FF, CS and SG.

Efficient 32-nm CNTFET-Based 1-Bit Adder: A Fast and Energy-Optimized Design

CNTFETs are a shows potential choice for traditional CMOS technology due to their potential for lesser power consumption and superior performance. In the present paper, a new 1-bit hybrid full adder has been deliberated and proposed using both pass transistor (PT) and transmission gate logics (TGL), which utilizes a total of 16 transistors. The combination of PT and TGL can lead to improved power efficiency, reduced delay, and enhanced circuit performance in various VLSI applications. For 0.9 V supply voltage at 32-nm CNTFET technology, the power consumption is 0.0748 μW, which is to be an exceptionally low value with a lesser delay of 7.586 Ps and the power-delay-product (PDP) of 0.5674 aJ. The results obtained from this analysis demonstrate the power efficiency, speed, and overall performance of the proposed full adder design. The combination of 32-nm CNTFET technology, deliberate circuit design choices, and the use of specific logic elements (CMOS inverters and strong transmission gates) contributes to the reported characteristics. Using a 0.9 V supply voltage and 32-nm Stanford CNTFET Model technology, the suggested 1-bit adder circuit's concert was investigated using the Mentor Graphics Tool. Finally, using the proposed 1-bit full adder circuit, an N-bit ripple carry adder (N=8, 16 &amp; 32) is implemented and demonstrated. The Simulation results of the 8-bit RCA with a power consumption of 0.373 μW, the delay is 16.852 Ps and the PDP is 6.2857 aJ. These results show that proposed RCA’s have better performance compared to the already reported designs in terms of performance, speed, and power economy.

Experimental and Model Analysis of the Thermal and Electrical Phenomenon of Arc Faults on the Electrode Pole of Lithium-Ion Batteries

Aiming at the electrical safety problem of a high-voltage lithium-ion battery system caused by an arc, and based on the establishment of a battery arc fault experimental platform, the evolution law of safety caused by an arc in the negative terminal of a battery system under different working conditions is discussed. On this basis, a battery arc evolution model based on magnetohydrodynamics is established to analyze the arc’s electro-thermal coupling characteristics to further obtain the distribution of the arc’s multi-physical field. The results show that the arc generated by the high-voltage grade battery pack will break down the cell’s shell and form a hole, resulting in electrolyte leakage. When the loop current is 10 A, the evolution law of arc voltage and current is basically the same under different supply voltages, charges, and discharges. The accuracy of the battery arc simulation model is verified by comparing the simulation with the experimental results. The research in this paper provides a theoretical basis for the electrical safety design of lithium-ion batteries caused by the arc, fills the gaps in the field of battery system arc simulation, and is of great significance for improving the safety performance of arc protection.

Positive Rail Voltage Rise Behavior and Inhibition Analysis of Regenerative Braking of Medium–Low-Speed Maglev Train

When a medium–low-speed (MLS) maglev train is braking, part of its regenerative braking (RB) power consumption may cause a significant rise in the positive rail (PR) voltage. For RB energy re-utilization, an RB energy feedback system (RBEFS) is a promising application, but there is still no specific research in the field of MLS maglev trains. From this perspective, this article focuses on identifying the PR voltage rise behavior and investigating the application of an RBEFS on the over-voltage inhibition. Some development trends of the MLS maglev train, including the DC 3 kV traction grid system and the speed being raised to 160~200 km/h, are also considered in the analyzed scenarios. At first, a modeling scheme of a detailed vehicle–grid electrical power model with the RBEFS is established. On this basis, the PR voltage rise characteristics are analyzed with consideration of three pivotal influencing factors: RB power, PR impedance and supply voltage level. Subsequently, to stabilize the PR voltage fluctuations, the influence rules of the RBEFS on the voltage rise and the mutual transient voltage influences under the operating status switching for multiple vehicles running on the same power supply section are analyzed.

A Two-Stage Sub-Threshold Voltage Reference Generator Using Body Bias Curvature Compensation for Improved Temperature Coefficient

Leakage diodes cause deviations in the thermal drift of ultra-low-power two-transistor (2T) reference circuits, resulting in either convex or concave output voltages against temperature, depending on the reference transistor types (n-type/p-type). This paper investigates the combined application of the convexity and concavity properties exhibited by the output voltage of complementary 2T references, one n-type and one p-type. By exploiting the body bias effect, this approach mitigates variations in the output reference voltage caused by temperature fluctuations. Software optimization is also used to obtain the required aspect ratios after formulating the required criteria for drain-induced barrier lowering (DIBL) elimination in the first stage. The performance of the proposed reference is evaluated by post-layout Monte Carlo simulations. In the range of 0 °C to 100 °C, the output reference voltage has an average temperature coefficient (TC) of 26.7 ppm/°C without any temperature trim. The output reference voltage is 195.5 mV with a standard deviation of 13.6 mV. The line sensitivity (LS) is 17.1 ppm/V in the supply voltage range of 0.5 V to 2.1 V at 25 °C. At 25 °C and 0.5 V, the power consumption is 28.8 pW, increasing to a maximum of 1.3 nW at 100 °C and 2.1 V.

A Novel DNA Synthesis Platform Design with High-Throughput Paralleled Addressability and High-Density Static Droplet Confinement.

Using DNA as the next-generation medium for data storage offers unparalleled advantages in terms of data density, storage duration, and power consumption as compared to existing data storage technologies. To meet the high-speed data writing requirements in DNA data storage, this paper proposes a novel design for an ultra-high-density and high-throughput DNA synthesis platform. The presented design mainly leverages two functional modules: a dynamic random-access memory (DRAM)-like integrated circuit (IC) responsible for electrode addressing and voltage supply, and the static droplet array (SDA)-based microfluidic structure to eliminate any reaction species diffusion concern in electrochemical DNA synthesis. Through theoretical analysis and simulation studies, we validate the effective addressing of 10 million electrodes and stable, adjustable voltage supply by the integrated circuit. We also demonstrate a reaction unit size down to 3.16 × 3.16 μm2, equivalent to 10 million/cm2, that can rapidly and stably generate static droplets at each site, effectively constraining proton diffusion. Finally, we conducted a synthesis cycle experiment by incorporating fluorescent beacons on a microfabricated electrode array to examine the feasibility of our design.

Deployment Actuator Logic Design for Enhancing Aircraft Armament Stability

For the high reliability of guidance weapon, it is important to maintain the stable supply voltage for guidance system while the bomb is gliding. However, the DC motor drive for guidance control in the low temperature can lead to the critical voltage drop due to a large inrush current.In this paper, we propose the wing deployment logic design to enhance the guidance system stability. To derive the stable drive logic based on PWM, we controlled the duty cycles for input voltage of DC motor in low temperature. The initial duty cycle was set to 40 % to relieve the inrush current. Moreover, the proper time, which is less than 1 second for controlling duty cycles, was determined by the iterative wing deployments of guidance kit. Finally, the validity of proposed logic was confirmed from the result the maximum voltage drop for the wing deployment was decreased by 23 %.