Supply Voltage Of Digital Circuits Research Articles

Minimum energy point tracking based on adaptive voltage scaling circuit

In order to realize the low-voltage and low-power dissipation designing of digital circuits, minimum energy point tracking (MEPT) based on adaptive voltage scaling (AVS) circuit is proposed in this paper. With process, voltage and temperature and frequency variance, the supply voltage of digital circuits is decreased dramatically by AVS, and equals to minimum voltage point (MVP), and advantageously in reducing dynamic energy consumption. Based on the MVP, in order to effectively decrease energy consumption of digital circuits, minimum energy point (MEP) of digital circuits is searched via comparing energy dissipation under different supply voltage by MEPT. Therefore, the supply voltage and energy consumption of digital circuits are decreased dramatically by the proposed novel circuit. The proposed circuit has been implemented and fabricated in a standard 0.18 μm CMOS process. The experimental results show that, when operating frequency of load keeps 1.319 MHz, the MVP and MEP of load are 425 and 450 mV, respectively. For operation frequency 5.334 MHz, the MEP changes from 625 to 550 mV with the degree of activity of load difference. Comparing with the traditional fixed voltage circuits, the maximum saving 91% of dynamic energy is realized by the proposed circuit.

An adaptive voltage scaling DC–DC converter based on embedded pulse skip modulation

An adaptive voltage scaling (AVS) DC---DC converter based on embedded pulse skip modulation (PSM) is presented in this paper. As AVS technique developing, the supply voltage of digital circuits can be scaled adaptively with the changing of operation frequency and working environment. The critical path replica (CPR) is widely used in AVS implementation. The worst-case margin is relaxed by probing and tracking the CPR delay time of target applications. Consequently, the energy consumption of digital circuits is decreased significantly with supply voltage reduced. At the same time, in order to improve the efficiency of DC---DC converter especially in light load, the PSM mode has been used in proposed circuit structure. The circuit of AVS DC---DC converter based on embedded PSM has been implemented and fabricated in a standard 0.13 μm CMOS process which occupies 1.2 mm2 active silicon areas. The experimental results show that, the output voltage of the DC---DC converter is well regulated from 0.6 to 1.5 V when the clock frequency varies within the range of 30---150 MHz. The maximum energy saving of 83 % is obtained with the proposed circuit structure compared to the traditional fixed voltage.

Comparison of in-situ delay monitors for use in Adaptive Voltage Scaling

Abstract. In Adaptive Voltage Scaling (AVS) the supply voltage of digital circuits is tuned according to the circuit's actual operating condition, which enables dynamic compensation to PVTA variations. By exploiting the excessive safety margins added in state-of-the-art worst-case designs considerable power saving is achieved. In our approach, the operating condition of the circuit is monitored by in-situ delay monitors. This paper presents different designs to implement the in-situ delay monitors capable of detecting late but still non-erroneous transitions, called Pre-Errors. The developed Pre-Error monitors are integrated in a 16 bit multiplier test circuit and the resulting Pre-Error AVS system is modeled by a Markov chain in order to determine the power saving potential of each Pre-Error detection approach.

A voltage-controlled oscillator with an ultra-low supply voltage and its application to a fractional-N phase-locked loop

With feature size scaling, the supply voltage of digital circuits is becoming lower and lower. As a result, the supply voltage of analogue and RF circuits must also be reduced for system on chip (SoC) realisation. This article proposes an ultra-low-supply voltage-controlled oscillator (ULSVCO) and designs a sigma–delta fractional-N frequency synthesiser which adopts such ULSVCO. A mathematical phase-noise model is built here to describe the noise performance of the low-supply voltage-controlled oscillator (VCO). The substrate of the cross-coupled NMOSFETs in the proposed ULSVCO is not grounded but connected to the supply to further reduce the supply voltage. Implemented in 0.18 μm CMOS technology, the proposed ULSVCO can be operated at a supply voltage as low as 0.41 V, the central frequency is set to 1.55 GHz, the phase noise is −116 dBc/Hz@1.0 MHz. The minimum supply voltage is decreased by about 11% after our idea is adopted and the power consumption of the ULSVCO is only 1.04 mW. With the proposed ULSVCO, we design a sigma–delta-modulator (SDM) fractional-N phase-locked loop frequency synthesiser, which has a 1.43–1.75 GHz frequency tuning range. When the loop bandwidth is set to 100 KHz, the phase noise of our PLL is −110 dBc/Hz@1.0 MHz.

Analysis of the Buck Converter for Scaling the Supply Voltage of Digital Circuits

The energy consumption in mobile systems has become a big challenge that limits high performance and autonomy in mobile systems. The dynamic voltage scaling (DVS) is a recent technique that reduces energy consumption varying dynamically the supply voltage of the system accordingly to the clock frequency. The Buck topology is a good candidate to supply step variations of the output voltage meeting the DVS requirements. In this paper, it is analyzed which is the fastest output voltage evolution that can provide the Buck topology. The minimum time state transition in the Buck converter and its corresponding control law are obtained applying the Maximum Principle or Pontryagin's Principle. Design criteria for the Buck topology are derived from this result. The analysis is extended to a multiphase Buck converter. The minimum time control law is validated in a prototype. The measurements are in good agreement with the theoretical results.