Following our work on simultaneous imaging of single-event-upsets (SEU) and single-event-latchups (SEL) in a static CMOS RAM with the GSI heavy ion microprobe [3], we tried to locate the addresses of the SEUs induced by a SEL event within one or more of the 8 bit-arrays on the chip. The result was that whenever we triggered a latchup by hitting a latchup-sensitive node, we always found multiple-SEU-events also in bit-arrays far away from the hit, although we made sure that the supply voltage drop during latchup (necessary to stop the latchup process and to prevent destruction of the chip) never went so low as to loose stored bits. Still more surprising we found these multiple-SEU-events also when we hit certain SEL-sensitive nodes though we did not detect SELs there. The reason for that process is still not fully understood [1], but the immediate lesson is that conventional, wide beam latchup tests of integrated circuits may largely underestimate the occurrence of latchups and their accompanying multiple-SEU-events which are a big problem for error detection and correction.