Superior Endurance Characteristics Research Articles

Impact of Dual-Gate Configuration on the Endurance of Ferroelectric Thin-Film Transistors With Nanosheet Polycrystalline-Silicon Channel Film

This work explores the characteristics of ferroelectric thin-film transistors (FeTFTs) utilizing an asymmetric dual-gate (DG) structure in both single-gate (SG) and DG operation modes. In the transfer characteristics, DG mode exhibits a memory window (MW) of 1.075 V, smaller than SG mode’s MW of 1.402 V, attributed to the back-gate bias effect causing a reduction in the device’s threshold voltage. However, DG mode demonstrates superior endurance characteristics with 106 cycles compared to SG mode’s 105 cycles. Additionally, the increase in erase pulse voltage (VERS) exacerbates the polycrystalline-silicon channel lattice damage of FeTFT, resulting in subthreshold swing (SS) degradation. Nevertheless, the extent of SS degradation from DG mode operation is significantly lower than that of SG mode, contributing to the superior endurance of DG mode. The elevation of program pulse voltage (VPRG) induces imprint and charge-trapping effects in the top-gate ferroelectric dielectric, leading to reduced endurance. Due to the use of SiO2 as the back-gate dielectric in FeTFT, DG mode exhibits lower impacts of charge-trapping effects from the top-gate ferroelectric dielectric layer, resulting in better endurance compared to SG mode. The asymmetric DG structure provides greater tolerance in the selection of VPRG and VERS.

Uniform resistive switching and highly stable synaptic characteristics of HfOx sandwiched TaOx-based memristor for neuromorphic system

Emerging nanoscale devices, including memristors, have been extensively studied to implement biological synaptic functions such as learning and plasticity, which are the fundamental building blocks of brain-inspired neuromorphic computing. The memristor with analog switching ability exhibits linear tuning of weight during neural network training is a desirable synaptic device behavior. The importance of inserting a HfOx sandwiched layer in a TaOx/HfOx/TaOx memristor is to achieve analog set/reset operation along with improved spatial/temporal switching uniformity. The optimal resistive switching (RS) behavior can be attributed to asymmetric oxygen vacancy distribution in the stacked structure leading to the formation of an hourglass-shaped conductive filament. Furthermore, confining filament formation/rapture in the narrow fixed region displays superior endurance characteristics (dc cycles >2000 and ac cycles > 106) and uniform resistive switching with the set (reset) voltage variation constrained to 1.8 (2.9) %. Paired-pulse facilitation (PPF), a form of short-term synaptic plasticity is stimulated to replicate bio-synapse behavior. The stable long-term potentiation (LTP) and depression (LTD) behavior for more than 1000 epochs (>105 pulses) with excellent symmetry and linearity is achieved with 50 ns voltage pulse stimulation. The pattern recognition accuracy of 93% was achieved for an image of size 10 × 10 pixels after 13 epochs by deploying 100 synapses in Hopfield Neural Network (HNN) simulation. This comprehensive study demonstrates that the HfOx-inserted TaOx memristor has tremendous potential for application in future neuromorphic computing.

Superior endurance performance of nonvolatile memory devices based on discrete storage in surface-nitrided Si nanocrystals

The surface-nitrided silicon nanocrystals (Si-NCs) floating gate nonvolatile memory (NVM) devices were fabricated by 0.13 μm node CMOS technology. The surface-nitrided Si-NCs were formed in-situ by low-pressure chemical vapor deposition and followed by nitridation treatment in NH3 ambient. It is found that the nitridation treatment not only enhances the control effect of gate voltage on channel carriers by passivation of the Si-NCs surface defects but also suppresses releasing of the stored carriers among the neighboring Si-NCs and leakage from Si-NCs to channel through the tunneling oxide by a silicon nitride cover layer acted as potential barrier. Consequently, the storage carriers are fully discrete in the Si-NCs, which are different from that in the conventional poly-crystal Si or SONOS floating gate NVM devices. The surface-nitrided Si-NCs NVM devices show lower subthreshold swing value of 0.13 V/decade, faster P/E speed characteristics of 1 μs at ±7 V, and good retention characteristics at room temperature. Furthermore, due to the improvement of the tunneling oxide quality by nitridation treatment, the stable memory window of 1.7 V has been kept after 107 P/E cycles, showing superior endurance characteristics with the good retention characteristics. Our fabrication of surface-nitrided Si-NCs floating gate NVM is compatible with the standard CMOS technology, which may be employed in the 3-D NAND technology to further improve the device performance.

Performance improvement of metal-Al2O3-HfO2-oxide-silicon memory devices with band-engineered Hf-aluminate/SiO2 tunnel barriers

Physical properties of Hf-aluminate (HA) films with various compositions, deposited by atomic layer deposition, were investigated in terms of microstructure, band-gap, and band-offset with respect to Si. Charge trap flash (CTF) memory devices based on HA/SiO2 stacks as tunnel barriers were also fabricated and characterized. Modulation of HA film composition produced controlled changes of the film's band-gap and band-offset. Additionally, the tunneling efficiency of the HA/SiO2 tunnel barrier stacks was observed to be higher than that for a single SiO2 tunnel barrier, in particular at high voltage bias. The band-engineered CTF memory devices with HA/SiO2 tunnel barriers showed improved program/erase speed compared with those with single SiO2 tunnel barrier. The Al-rich HA/SiO2 tunnel barriers showed a longer charge retention time with superior endurance characteristics; in contrast, the Hf-rich HA/SiO2 tunnel barrier showed degraded charge retention because of current leakage through crystallized regions in the film.

High-Reliability Dynamic-Threshold Source-Side Injection for 2-Bit/Cell With MLC Operation of Wrapped Select-Gate SONOS in nor-Type Flash Memory

For the first time, a high-performance (τPGM = 200 ns/τERS = 5 ms) cell with superior reliability characteristics is demonstrated in a nor-type architecture, using dynamic-threshold source-side injection (DTSSI) in a wrapped select-gate silicon-oxide-nitride-oxide-silicon memory device, with multilevel and 2-bit/cell operation. Using DTSSI enables easy extraction of the multilevel states with a tight VTH distribution, a nearly negligible second-bit effect, superior endurance characteristics, and good data retention.

Silicon-oxide-high-κ-oxide-silicon memory using a high-κ Y2O3 nanocrystal film for flash memory application

In this article, the authors developed a silicon-oxide-high-κ-oxide-silicon (SOHOS) memory structure using a high-κ Y2O3 nanocrystal film as the charge-trapping layer for flash memory applications. From x-ray photoelectron spectroscopic and atomic-force microscopy analyses, they found that the Y2O3 nanocrystal layer formed after O2 and N2O annealing. When using the channel hot-electron injection for charging and the band-to-band hot hole for discharging, the high-κ Y2O3 SOHOS memory devices prepared under the N2O gas annealing exhibited large threshold-voltage shifting (memory window of ∼3V), superior endurance characteristics (program/erase cycles of up to 105), and excellent data retention (charge loss of ∼7.5% measured time up to 104s and at room temperature). These results indicate the higher probability of charge-carrier trapping in the Y2O3 film.

High-Performance High-$k$$\hbox{Y}_{2}\hbox{O}_{3}$ SONOS-Type Flash Memory

In this paper, we propose a novel high-k Y <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> poly-Si-oxide-nitride-oxide-silicon (SONOS)-type flash memory. The structural and morphological features of Y <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> films were studied using atomic force microscopy, transmission electron microscopy, and X-ray photoelectron spectroscopy. These high-k Y <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> SONOS-type memories exhibited large threshold voltage shifting (memory window of 1.9-4.33 V), almost negligible read and gate disturb (threshold voltage shift of ~2-mV operation at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = 3 V and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> = 4 V and ~4-mV operation at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> =8 V, respectively), excellent data retention (charge loss of ~4% measured time up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> s and at room temperature, expected ~22% charge loss for ten years at 125degC), and superior endurance characteristics (program/erase cycles up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> ) because of the higher probability for trapping charge carriers. These Y <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> films appear to be a very promising charge trapping layer for high-density two-bit nonvolatile flash memory applications.

Polysilicon–Oxide–Nitride–Oxide–Silicon-Type Flash Memory Using an Y[sub 2]O[sub 3] Film as a Charge Trapping Layer

A polysilicon-oxide-nitride-oxide-silicon-type flash memory using a high-k yttrium oxide (Y 2 O 3 ) film as the trapping storage layer is developed. This high-k Y 2 O 3 charge trapping layer memory exhibited large threshold voltage shifting (memory window of 3 V), excellent data retention (charge loss of 5 and 10% measured time up to 10 4 s and recorded at room temperature and 125°C, respectively), and superior endurance characteristics (program/erase cycles up to 10 5 ) because of the higher probability for trapping the charge carrier. This film appears to be a very promising charge trapping layer for high-density, two-bit nonvolatile flash memory application.

Scanning capacitance microscopy measurements using diamond-coated probes

Diamond-coated cantilevers have been used for scanning capacitance microscopy (SCM) as an alternative for metal-coated cantilevers in order to improve the stability of probes. It is shown that the diamond-coated probes produce adequate intensity of dC signal and high contrast for both p-type and n-type silicon samples and also provide superior endurance characteristics to metal-coated probes. Due to the robustness of the diamond-coated probes, we are able to evaluate the reproducibility of measurements and the homogeneity of the ultrathin oxide for both dry oxidation (heated up to 300 °C in air under ultraviolet illumination) and wet oxidation (immersed into a hydrogen peroxide solution at 70 °C). The dry oxidation shows better reproducibility, while the wet oxidation shows better homogeneity. Finally, comparison of SCM with secondary ion mass spectrometry measurement shows that diamond-coated probes can be used at least for one-dimensional quantitative SCM measurements without any significant effect of depletion in the diamond-coated tip itself.