Superconducting Single Flux Quantum Research Articles

Generating Microwave Signals with Enhancive Amplitudes Using Superconductor Single Flux Quantum Pulses for Controlling Quantum Bit

AbstractIn this study, the on‐chip generation of microwave signals are proposed for controlling nearby quantum bits in a low‐temperature environment, utilizing superconducting logical and RF components. To achieve enhanced amplitude of the microwave, superconducting single flux quantum (SFQ) pulse pairs are employed, which can have either the same or reversal polarity, serving as the basic elements of the generator. The SFQ pulse pairs are then combined and wave‐shaped by using a microwave combining filter, which finally outputs desired microwave signals with narrow line‐width. The amplitude of the microwave signal correlates with the interval between two SFQ pulses in a pair and can be adjusted accordingly. To validate the proposal, test chips are fabricated and performed experiments. The experimental results confirm that the method using a reverse‐polarity pulse can maximize the output microwave amplitude and provide control of the initial phase of the output microwave. This improvement offers a superior alternative for generating microwaves using superconducting circuits to control quantum bits.

Amplitude-controllable microwave pulse generator using single-flux-quantum pulse pairs for qubit control

To achieve large-scale quantum processors, cryogenic quantum-bit (qubit) interface circuits that can control qubits inside a dilution refrigerator are indispensable. Superconducting single-flux quantum (SFQ) circuits are a promising building block for qubit interface circuits because SFQ circuits can operate with high clock frequencies and low power dissipation. In the present study, we developed an SFQ-based qubit interface circuit that we refer to as a pulse-pair microwave pulse generator (PP-MPG). The PP-MPG can generate microwave pulses for qubit control, with the microwave amplitude controlled based on the delay between paired SFQ pulses. By finely adjusting the delay with delay controlling circuits, the microwave amplitude can be controlled over a wide range. We fabricated a PP-MPG chip and tested it at 4.2 K, showing that the microwave amplitude can be controlled over a range of approximately 30 dB. Our results show that the PP-MPG has the potential for use in future large-scale quantum processors.

Low power single flux quantum qubit control circuit without high-frequency input

The use of high-frequency input signals from room-temperature microwave sources makes it difficult to scale up the number of quantum bits in universal quantum computers. To address this issue, superconducting single flux quantum (SFQ) integrated circuits are being explored as suitable candidates for qubit manipulation in universal quantum computers. This paper deals with a scalable SFQ qubit control circuit (SQCC) structure that requires only low-frequency input. The circuit mainly consists of a pulse generator and a counter, that output the SFQ pulse train with adjustable frequency and a controllable number of pulses, which is applicable to control single-qubit Clifford operations. The design of low-voltage rapid single flux quantum (LV-RSFQ) and energy-efficient rapid single flux quantum (ERSFQ) for the SQCC achieves low power consumption and provides a basis for scaling up SQCC to control more qubits. The proposed circuits are fabricated under the SIMIT-Nb03 process and successfully pass test verification. The achieved test results reveal that the adjustable output frequency ranges of the SQCC based on the LV-RSFQ and ERSFQ designs in order are [2.40, 8.11] GHz and [4.81, 5.14] GHz. In the operating frequency range, the circuit is able to generate the correct number of SFQ pulses under control. The controllable number range is from 1 to 128. When the circuits operate at 5 GHz, the total power consumptions of the above circuits in order are 23.88 μW and 6.2 μW. All input signals are low-frequency signals, which frees the control of large-scale qubits from limitations caused by high-frequency inputs produced by room-temperature microwave sources.

Evaluation of True Random Number Sequences Generated by Utilizing Timing Jitters in Superconducting Integrated Circuits

A Hardware Random Number Generator (HRNG), which generates true random number sequences, is studied. In superconducting Single Flux Quantum (SFQ) circuitry, HRNGs that utilized timing jitters in trigger signals have been demonstrated. In this paper, we propose an HRNG with two oscillators to enhance stability against variation of oscillator frequencies. We investigate the characteristics of random numbers generated with the proposed HRNG not only by numerical simulation but also by experiments using Nb test circuits. In the numerical simulation, the probability of “1” in random number sequences has a local minimum of “1” output probability at conditions where fclk (the clock oscillator frequency) and fgate (the gate oscillator frequency) are approximately equal (fclk ≈ fgate ) for fclk ≤ 60 GHz. It is also found that pass rates for the FIPS140-2 random number tests are little affected by variations of fclk at fgate = 69.2 GHz. The random number generation rate for fclk = 60 GHz and fgate = 43 GHz reaches 3.98 GHz. In experimental measurements, random numbers of 1 Mbits generated by a test circuit pass the SP800-22 random number tests at fclk = 48.79 GHz and fgate = 19.81 GHz.

Cryogenic memory technologies

The surging interest in quantum computing, space electronics, and superconducting circuits has led to new developments in cryogenic data storage technology. Quantum computers promise to far extend our processing capabilities and may allow solving currently intractable computational challenges. Even with the advent of the quantum computing era, ultra-fast and energy-efficient classical computing systems are still in high demand. One of the classical platforms that can achieve this dream combination is superconducting single flux quantum (SFQ) electronics. A major roadblock towards implementing scalable quantum computers and practical SFQ circuits is the lack of suitable and compatible cryogenic memory that can operate at 4 Kelvin (or lower) temperature. Cryogenic memory is also critically important in space-based applications. A multitude of device technologies have already been explored to find suitable candidates for cryogenic data storage. Here, we review the existing and emerging variants of cryogenic memory technologies. To ensure an organized discussion, we categorize the family of cryogenic memory platforms into three types: superconducting, non-superconducting, and hybrid. We scrutinize the challenges associated with these technologies and discuss their future prospects.

Static Timing Analysis for Single-Flux-Quantum Circuits Composed of Various Gates

Superconductive single-flux-quantum (SFQ) circuits operate with very high clock frequency and its timing design is a difficult task. In circuit design, static timing analysis (STA) is a key process for evaluating and verifying the timing of a circuit design. Conventional timing analysis for SFQ circuits focuses on circuits composed of clocked gates and splitters; however, practical SFQ circuits are composed of various gates, i.e., not only clocked gates but also other gates, such as nondestructive read-out, confluence buffer, and clockless logic gates. In this article, to express timing constraints of both clocked gate cells and other cells, we define timing requirements of cells as minimum and maximum acceptable intervals on ordered pairs of input pins. Via these, we express timing constraints of cells in an SFQ circuit design. Furthermore, to eliminate unnecessary pessimism during variation-aware timing analysis, we propose a method of common path pessimism removal (CPPR) for SFQ circuits composed of various cells. We implement an STA tool using the defined timing constraints and the CPPR method. The experimental results show that our STA tool verifies the timing of SFQ circuits composed of various cells.

Superconducting single flux quantum (SFQ) technology for power-efficiency computing

Superconducting single flux quantum (SFQ) technology for power-efficiency computing

JBNN: A Hardware Design for Binarized Neural Networks using Single-Flux-Quantum Circuits

As a high-performance application of low-temperature superconductivity, superconducting single-flux-quantum (SFQ) circuits have high speed and low-power consumption characteristics, which have recently received extensive attention, especially in the field of neural network inference accelerations. Despite these promising advantages, they are still limited by storage capacity and manufacture reliability, making them unfriendly for feedback loops and very large-scale circuits. The Binarized Neural Network (BNN), with minimal memory requirements and no reliance on multiplication, is undoubtedly an attractive candidate for implementing inference hardware using SFQ circuits. This work presents the first SFQ-based Binarized Neural Network inference accelerator, namely JBNN, with a new representation to binarize weights and activation variables. Every SFQ gate is essentially a pipeline stage, making conventional design methods of the accumulator unsuitable for SFQ circuits. So an SFQ-based accumulative parallel counter using SFQ logic cells including T1, OR, and AND is designed to realize the accumulation, where the data size is reduced to a quarter after passing the XNOR column and the AU layer, largely declining the hardware cost. Our evaluation shows that the proposed design outperforms a cryogenic CMOS-based BNN accelerator design running at 77K by 70.92 times while maintaining 97.89% accuracy on the MNIST benchmark dataset. Without the cooling cost, the power efficiency increases up to 929.18 times.

YBa$_{2}$Cu$_{3}$O$_{7-\delta }$Single Flux Quantum Flip Flop Directly Written With a Focused Helium Ion Beam

Superconducting logic circuits based on low transition temperature (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> ) are attractive due to their intrinsic low power consumption and high operating frequency. They have a wide variety of applications (particularly in future computing), but are difficult to use because they require cooling with liquid helium to operate. The current high T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> logic circuit based on YBa <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7-δ</sub> (YBCO) already has the ability to operate at a temperature above 4 K. However, this material is difficult to integrate into large-scale circuits by the traditional YBCO junction fabrication process. The limits of fabrication methods are the bottleneck stifling this material's potential for integration into logic circuits. As such, in this paper we aim to advance the state of the art in junction fabrication technology. Here we report the demonstration of a high T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> superconducting single flux quantum (SFQ) circuit made by a focused helium ion beam that is easily fabricated and can readily be incorporated into a large-scale integration with nano-scale junctions for future applications. An inductively coupled readout superconducting quantum interference device (SQUID) is employed to reduce the circuit complexity. The circuit parameters and performance are discussed.

Multilayer magnetic shielding for testing a superconducting single-flux-quantum circuit chip in liquid helium dewar

In order to reduce the influence of environmental magnetic field on the test of superconducting single-flux-quantum (SFQ) circuit chip in a liquid helium dewar, a multilayer magnetic shielding structure is designed to provide a clean magnetic field lower than 50 nT and achieve a shielding effectiveness higher than 60 dB. The magnetic shielding structure consists of three cylindrical layers with uniform 1 mm thickness. The first inner layer is made of NbTi which works as a strong diamagnet shell, while the outer two layers are made of permalloy which has high permeability at helium temperature. The superconducting quantum interference device (SQUID) was used to test the shielding performance of the structure under low frequency (0.1–100 Hz) magnetic interference at helium temperature. The results show that the radial and axial shielding effectiveness (SE) are about 80 dB and 68 dB, respectively, indicating that the multilayer structure has good shielding performance and can be used in the testing system of superconducting single-flux-quantum circuit chip.

Depth-bounded Graph Partitioning Algorithm and Dual Clocking Method for Realization of Superconducting SFQ Circuits

Superconducting Single Flux Quantum (SFQ) logic with switching delay of 1ps and switching energy of 10 −19 J is a potential emerging candidate for replacing Complementary Metal Oxide Semiconductor (CMOS) to achieve very high speed and ultra energy efficiency. Conventional SFQ circuits need Full Path Balancing (FPB), which tends to require insertion of many path balancing buffers (D-Flip-Flops). FPB method increases total power consumption as well as total area of the chip. This article presents a novel scheme for realization of superconducting SFQ circuits by introducing a new depth-bounded graph partitioning algorithm in combination with a dual clocking method (slow and fast clock pulses) that minimizes the aforesaid path balancing overheads. Experimental results show that the proposed solution reduces total number of path balancing buffers and total static power consumption by an average of 2.68× and 60%, respectively, when compared to the best of other methods for realizing SFQ circuits. However, our scheme degrades the peak throughput; therefore, it is especially valuable when the actual throughput of the SFQ circuit is much lower than the peak theoretical throughput. This is typically the case due to high-level data dependencies of the application that feeds data into an SFQ circuit.

QSTA: A Static Timing Analysis Tool for Superconducting Single-Flux-Quantum Circuits

Superconducting single-flux-quantum (SFQ) technology is a beyond-complementary metal–oxide–semiconductor (CMOS) technology, promising ultrahigh processing speed and low power consumption. A timing analysis tool for SFQ circuits should check circuit timing behavior, including working frequencies and hold time violations to determine the circuit performance. Unlike CMOS gates, generic SFQ gates are clocked gates, which produce their output pulses in response to a clock pulse and have a fan-out capability of one. An SFQ splitter, a special clockless gate that has a fan-out capability of two, is used to address the fan-out limitation. This gate is also utilized in the clock tree, which distributes clock pulses to various SFQ gates. The delay of a clock path in a clock tree is determined by the wire delays of connection nets and gate delays of splitters. However, the splitter delays in a clock path are significantly affected by process variations, resulting in a challenging skew problem. Furthermore, existing timing analysis tools of SFQ circuits are developed based on the timing definitions, rules, and constraints from CMOS technology with very few modifications. This article demonstrates the incompleteness of the existing SFQ technology timing definitions. Precisely, it presents a novel static timing analysis (STA) tool, qSTA, which checks the timing behavior of SFQ circuits based on revised definitions of the setup time and hold times. qSTA encompasses the common path pessimism removal technique, which removes the delays of the shared path segments between two clock paths to achieve a better approximation of real skew values. qSTA takes only 5.33 s to check the timing behavior of a 16-bit integer divider with 36 732 gates and 55 939 nets.

QSSTA: A Statistical Static Timing Analysis Tool for Superconducting Single-Flux-Quantum Circuits

Superconducting single flux quantum (SFQ) technology is an ultra-high performance and low power technology. The technology, however, lacks many of the design automation tools and capabilities that are commonplace in CMOS technology. This article describes methods to efficiently find the conditional probability density function (PDF) of the minimum workable clock period of SFQ circuits in view of manufacturing-induced process variations and presents qSSTA, a statistical static timing analysis tool targeting SFQ circuits. Following a grid-based correlation model, qSSTA represents spatial correlation of SFQ gates at different positions with respect to process parameters. By approximating timing characteristics of SFQ gates in a linear model, qSSTA is able to estimate the clock period as a normal random variable. Furthermore, process variations that generally result in extra delays in CMOS circuits can result in functional errors in SFQ circuits. qSSTA derives the closed form of the conditional PDF of the clock period under the scenario where all SFQ gates in the circuit work correctly. Compared to Monte Carlo simulations on look-up tables, experimental results show that the average percentage errors are 0.89% for the mean values, 8.04% for the standard deviation, and 0.61% for the 98-percentile point, whereas the runtime of qSSTA is 83% faster on average.

Timing Jitter Characterization of the SFQ Coincidence Circuit by Optically Time-Controlled Signals From SSPDs

We report on the timing jitter characterization of the superconducting single flux quantum (SFQ) coincidence circuit, which is an essential component of the superconducting coincidence photon counter. Two superconducting nanowire single photon detectors (SSPDs), each of which is irradiated with optically time-controlled photons, are connected to the SFQ coincidence circuit, and the timing jitter of the SFQ circuit is evaluated by changing the relative time delay between two input ports for the SFQ comparator unit. We successfully observe the transition curve of the probability of obtaining the signal from the SFQ coincidence circuit by sweeping photon arrival time to each SSPD and confirm that this curve shifts temporally upon changing the bias current to the Josephson transmission line (JTL) in the SFQ circuit. A systematic investigation reveals that the relation between time delay and the bias current to JTL can be estimated. The full width half maximum timing jitter of the SFQ circuit is 1.1 ps, which is sufficiently low so that it does not influence the entire timing jitter of the coincidence photon counter.

Research on the Bias Network of Energy-Efficient Single Flux Quantum Circuits

Superconducting single flux quantum (SFQ) circuits have been shown to offer huge advantages that are ideal for high performance computing applications. These circuits can operate at very high frequencies (tens of GHz) but consume very low power (from nanowatts to microwatts per gate). Energy-efficient SFQ (ERSFQ) circuits, evolved from traditional rapid SFQ (RSFQ) circuits, were invented with the goal of elimination of static power dissipation. When compared with RSFQ circuits, ERSFQ circuits require a new biasing network that includes biasing Josephson junction(s), biasing inductor(s), and feeding Josephson transmission line(s). Some general suggestions on how to design the network have been offered, but a detailed analysis and optimization scenario for the network is still to be provided. In this paper, we first optimize the previously reported DC-biased two-Josephson junction per bit RSFQ shift register circuit, which can be used to provide a more robust, energy-efficient, and high memory capacity storage unit. The simulated power dissipation of 16-bit RSFQ shift register is 0.45 μW per bit when operating at 21.7 GHz. We then convert the RSFQ-based shift register into an ERSFQ structure and investigate the effects of the ERSFQ bias network on the margins of the ERSFQ circuit. Finally, we propose a more comprehensive optimization method for the ERSFQ biasing network.

Design for Testability of SFQ Circuits

Test point insertion and set/scan techniques for enhanced testability in superconductive single-flux-quantum (SFQ) logic are proposed here. Test point insertion reduces the overhead of a set/scan chain while maintaining most of the functionality. Multiple ways of replacing costly (in terms of the number of Josephson junctions) SFQ multiplexers with mergers and blocking gates are proposed. The multiplexer control signals are replaced with a gated clock signal or separate bias networks for both functional and test paths. Clocked blocking gates or current-controlled Josephson transmission line segments are used to disable undesired data inputs. The clocked blocking gates for test point insertion in a 64-bit register requires 35% fewer Josephson junctions as compared to multiplexers. This advantage further increases for current-controlled blocking gates. Set/scan chain and test point insertion techniques are applied to several SFQ circuits to evaluate error characteristics and to provide built-in self-test of SFQ-compatible memory systems.

9 bit superconductive single‐flux‐quantum digital‐to‐analogue converter

The design and operation of a 9 bit superconductive single-flux-quantum (SFQ) digital-to-analogue converter (DAC) are presented. The DAC comprises a 9 bit variable SFQ pulse number multiplier and a 100-fold voltage multiplier. An SFQ pulse-frequency modulation technique is employed for coding the analogue output voltage. The DAC is fabricated using an Nb Josephson integration technology. Its output voltage waveform, the amplitude of which is up to 2.54 mV pp, is controlled by digital input signals from a room-temperature data generator.

Optimization of SFQ Logic Gate Considering Dependence of its Signal Propagation Delay on the Bias Voltage

Superconductive single flux quantum (SFQ) digital circuits can operate at a clock frequency of several tens of gigahertz. The operating margin of an SFQ logic circuit generally decreases with an increase in the operating frequency because of the timing error in the low-bias region caused by the difference in bias dependence of the signal-propagation delay between the data and clock lines. We proposed an improvement in the operating margin by controlling the dependence of the signal-propagation time on the bias voltage. In the present study, we investigated a new optimization method for an SFQ logic gate. We developed a new circuit parameter optimizer, which takes into account not only the bias margin but also the dependence of the signal-propagation delay on the bias voltage. We defined an appropriate evaluation function for the optimization. From the result of the optimization using the defined evaluation function, we designed and demonstrated an SFQ AND gate optimized using the new optimizer.

Circuit Description and Design Flow of Superconducting SFQ Logic Circuits

Superconducting Single-Flux-Quantum (SFQ) devices have been paid much attention as alternative devices for digital circuits, because of their high switching speed and low power consumption. For large-scale circuit design, the role of computer-aided design environment is significant. As the characteristics of the SFQ devices are different from conventional devices, a new design environment is required. In this paper, we propose a new timing-aware circuit description method which can be used for SFQ circuit design. Based on the description and the dedicated algorithms we have been developing for SFQ logic circuit design, we propose an integrated design flow for SFQ logic circuits. We have designed a circuit using our developed design tools along with the design flow and demonstrated the correct operation. key words: single-flux-quantum circuit, design methodology, circuit description, logic design, layout design, design verification

Improvement of Operating Margin of SFQ Circuits by Controlling Dependence of Signal Propagation Time on Bias Voltage

Superconductive single flux quantum (SFQ) digital circuits can operate at a clock frequency of several tens of gigahertz. However, the operating margin of these circuits decreases with an increase in the operating frequency because a timing error occurs in the low bias region. In this study, a novel design method that enables a wide operating margin at a high operating frequency has been investigated. The proposed circuits incorporate an additional bias feeding line in addition to the conventional bias feeding lines of the conventional Josephson transmission lines (JTLs) and can control the dependence of signal propagation time on the bias voltage. We have shown experimentally that in our proposed JTLs, the signal propagation time becomes more sensitive to the bias voltage. Timing errors can be avoided by inserting proposed JTL cells in the critical data path of the SFQ digital circuits. Circuit simulation results indicate that the operating margin of a bit-serial SFQ full adder, designed assuming the 2.5 kA/cm2 Nb process, can be improved by 15% compared with the conventional design at a frequency of 20 GHz by employing our novel design method.