Design for Testability of SFQ Circuits

Abstract

Test point insertion and set/scan techniques for enhanced testability in superconductive single-flux-quantum (SFQ) logic are proposed here. Test point insertion reduces the overhead of a set/scan chain while maintaining most of the functionality. Multiple ways of replacing costly (in terms of the number of Josephson junctions) SFQ multiplexers with mergers and blocking gates are proposed. The multiplexer control signals are replaced with a gated clock signal or separate bias networks for both functional and test paths. Clocked blocking gates or current-controlled Josephson transmission line segments are used to disable undesired data inputs. The clocked blocking gates for test point insertion in a 64-bit register requires 35% fewer Josephson junctions as compared to multiplexers. This advantage further increases for current-controlled blocking gates. Set/scan chain and test point insertion techniques are applied to several SFQ circuits to evaluate error characteristics and to provide built-in self-test of SFQ-compatible memory systems.