Superconducting Single Flux Quantum Circuits Research Articles

Amplitude-controllable microwave pulse generator using single-flux-quantum pulse pairs for qubit control

To achieve large-scale quantum processors, cryogenic quantum-bit (qubit) interface circuits that can control qubits inside a dilution refrigerator are indispensable. Superconducting single-flux quantum (SFQ) circuits are a promising building block for qubit interface circuits because SFQ circuits can operate with high clock frequencies and low power dissipation. In the present study, we developed an SFQ-based qubit interface circuit that we refer to as a pulse-pair microwave pulse generator (PP-MPG). The PP-MPG can generate microwave pulses for qubit control, with the microwave amplitude controlled based on the delay between paired SFQ pulses. By finely adjusting the delay with delay controlling circuits, the microwave amplitude can be controlled over a wide range. We fabricated a PP-MPG chip and tested it at 4.2 K, showing that the microwave amplitude can be controlled over a range of approximately 30 dB. Our results show that the PP-MPG has the potential for use in future large-scale quantum processors.

Cryogenic memory technologies

The surging interest in quantum computing, space electronics, and superconducting circuits has led to new developments in cryogenic data storage technology. Quantum computers promise to far extend our processing capabilities and may allow solving currently intractable computational challenges. Even with the advent of the quantum computing era, ultra-fast and energy-efficient classical computing systems are still in high demand. One of the classical platforms that can achieve this dream combination is superconducting single flux quantum (SFQ) electronics. A major roadblock towards implementing scalable quantum computers and practical SFQ circuits is the lack of suitable and compatible cryogenic memory that can operate at 4 Kelvin (or lower) temperature. Cryogenic memory is also critically important in space-based applications. A multitude of device technologies have already been explored to find suitable candidates for cryogenic data storage. Here, we review the existing and emerging variants of cryogenic memory technologies. To ensure an organized discussion, we categorize the family of cryogenic memory platforms into three types: superconducting, non-superconducting, and hybrid. We scrutinize the challenges associated with these technologies and discuss their future prospects.

Static Timing Analysis for Single-Flux-Quantum Circuits Composed of Various Gates

Superconductive single-flux-quantum (SFQ) circuits operate with very high clock frequency and its timing design is a difficult task. In circuit design, static timing analysis (STA) is a key process for evaluating and verifying the timing of a circuit design. Conventional timing analysis for SFQ circuits focuses on circuits composed of clocked gates and splitters; however, practical SFQ circuits are composed of various gates, i.e., not only clocked gates but also other gates, such as nondestructive read-out, confluence buffer, and clockless logic gates. In this article, to express timing constraints of both clocked gate cells and other cells, we define timing requirements of cells as minimum and maximum acceptable intervals on ordered pairs of input pins. Via these, we express timing constraints of cells in an SFQ circuit design. Furthermore, to eliminate unnecessary pessimism during variation-aware timing analysis, we propose a method of common path pessimism removal (CPPR) for SFQ circuits composed of various cells. We implement an STA tool using the defined timing constraints and the CPPR method. The experimental results show that our STA tool verifies the timing of SFQ circuits composed of various cells.

JBNN: A Hardware Design for Binarized Neural Networks using Single-Flux-Quantum Circuits

As a high-performance application of low-temperature superconductivity, superconducting single-flux-quantum (SFQ) circuits have high speed and low-power consumption characteristics, which have recently received extensive attention, especially in the field of neural network inference accelerations. Despite these promising advantages, they are still limited by storage capacity and manufacture reliability, making them unfriendly for feedback loops and very large-scale circuits. The Binarized Neural Network (BNN), with minimal memory requirements and no reliance on multiplication, is undoubtedly an attractive candidate for implementing inference hardware using SFQ circuits. This work presents the first SFQ-based Binarized Neural Network inference accelerator, namely JBNN, with a new representation to binarize weights and activation variables. Every SFQ gate is essentially a pipeline stage, making conventional design methods of the accumulator unsuitable for SFQ circuits. So an SFQ-based accumulative parallel counter using SFQ logic cells including T1, OR, and AND is designed to realize the accumulation, where the data size is reduced to a quarter after passing the XNOR column and the AU layer, largely declining the hardware cost. Our evaluation shows that the proposed design outperforms a cryogenic CMOS-based BNN accelerator design running at 77K by 70.92 times while maintaining 97.89% accuracy on the MNIST benchmark dataset. Without the cooling cost, the power efficiency increases up to 929.18 times.

Depth-bounded Graph Partitioning Algorithm and Dual Clocking Method for Realization of Superconducting SFQ Circuits

Superconducting Single Flux Quantum (SFQ) logic with switching delay of 1ps and switching energy of 10 −19 J is a potential emerging candidate for replacing Complementary Metal Oxide Semiconductor (CMOS) to achieve very high speed and ultra energy efficiency. Conventional SFQ circuits need Full Path Balancing (FPB), which tends to require insertion of many path balancing buffers (D-Flip-Flops). FPB method increases total power consumption as well as total area of the chip. This article presents a novel scheme for realization of superconducting SFQ circuits by introducing a new depth-bounded graph partitioning algorithm in combination with a dual clocking method (slow and fast clock pulses) that minimizes the aforesaid path balancing overheads. Experimental results show that the proposed solution reduces total number of path balancing buffers and total static power consumption by an average of 2.68× and 60%, respectively, when compared to the best of other methods for realizing SFQ circuits. However, our scheme degrades the peak throughput; therefore, it is especially valuable when the actual throughput of the SFQ circuit is much lower than the peak theoretical throughput. This is typically the case due to high-level data dependencies of the application that feeds data into an SFQ circuit.

QSTA: A Static Timing Analysis Tool for Superconducting Single-Flux-Quantum Circuits

Superconducting single-flux-quantum (SFQ) technology is a beyond-complementary metal–oxide–semiconductor (CMOS) technology, promising ultrahigh processing speed and low power consumption. A timing analysis tool for SFQ circuits should check circuit timing behavior, including working frequencies and hold time violations to determine the circuit performance. Unlike CMOS gates, generic SFQ gates are clocked gates, which produce their output pulses in response to a clock pulse and have a fan-out capability of one. An SFQ splitter, a special clockless gate that has a fan-out capability of two, is used to address the fan-out limitation. This gate is also utilized in the clock tree, which distributes clock pulses to various SFQ gates. The delay of a clock path in a clock tree is determined by the wire delays of connection nets and gate delays of splitters. However, the splitter delays in a clock path are significantly affected by process variations, resulting in a challenging skew problem. Furthermore, existing timing analysis tools of SFQ circuits are developed based on the timing definitions, rules, and constraints from CMOS technology with very few modifications. This article demonstrates the incompleteness of the existing SFQ technology timing definitions. Precisely, it presents a novel static timing analysis (STA) tool, qSTA, which checks the timing behavior of SFQ circuits based on revised definitions of the setup time and hold times. qSTA encompasses the common path pessimism removal technique, which removes the delays of the shared path segments between two clock paths to achieve a better approximation of real skew values. qSTA takes only 5.33 s to check the timing behavior of a 16-bit integer divider with 36 732 gates and 55 939 nets.

QSSTA: A Statistical Static Timing Analysis Tool for Superconducting Single-Flux-Quantum Circuits

Superconducting single flux quantum (SFQ) technology is an ultra-high performance and low power technology. The technology, however, lacks many of the design automation tools and capabilities that are commonplace in CMOS technology. This article describes methods to efficiently find the conditional probability density function (PDF) of the minimum workable clock period of SFQ circuits in view of manufacturing-induced process variations and presents qSSTA, a statistical static timing analysis tool targeting SFQ circuits. Following a grid-based correlation model, qSSTA represents spatial correlation of SFQ gates at different positions with respect to process parameters. By approximating timing characteristics of SFQ gates in a linear model, qSSTA is able to estimate the clock period as a normal random variable. Furthermore, process variations that generally result in extra delays in CMOS circuits can result in functional errors in SFQ circuits. qSSTA derives the closed form of the conditional PDF of the clock period under the scenario where all SFQ gates in the circuit work correctly. Compared to Monte Carlo simulations on look-up tables, experimental results show that the average percentage errors are 0.89% for the mean values, 8.04% for the standard deviation, and 0.61% for the 98-percentile point, whereas the runtime of qSSTA is 83% faster on average.

Research on the Bias Network of Energy-Efficient Single Flux Quantum Circuits

Superconducting single flux quantum (SFQ) circuits have been shown to offer huge advantages that are ideal for high performance computing applications. These circuits can operate at very high frequencies (tens of GHz) but consume very low power (from nanowatts to microwatts per gate). Energy-efficient SFQ (ERSFQ) circuits, evolved from traditional rapid SFQ (RSFQ) circuits, were invented with the goal of elimination of static power dissipation. When compared with RSFQ circuits, ERSFQ circuits require a new biasing network that includes biasing Josephson junction(s), biasing inductor(s), and feeding Josephson transmission line(s). Some general suggestions on how to design the network have been offered, but a detailed analysis and optimization scenario for the network is still to be provided. In this paper, we first optimize the previously reported DC-biased two-Josephson junction per bit RSFQ shift register circuit, which can be used to provide a more robust, energy-efficient, and high memory capacity storage unit. The simulated power dissipation of 16-bit RSFQ shift register is 0.45 μW per bit when operating at 21.7 GHz. We then convert the RSFQ-based shift register into an ERSFQ structure and investigate the effects of the ERSFQ bias network on the margins of the ERSFQ circuit. Finally, we propose a more comprehensive optimization method for the ERSFQ biasing network.

Timing Jitter Characterization of the SFQ Coincidence Circuit by Optically Time-Controlled Signals From SSPDs

We report on the timing jitter characterization of the superconducting single flux quantum (SFQ) coincidence circuit, which is an essential component of the superconducting coincidence photon counter. Two superconducting nanowire single photon detectors (SSPDs), each of which is irradiated with optically time-controlled photons, are connected to the SFQ coincidence circuit, and the timing jitter of the SFQ circuit is evaluated by changing the relative time delay between two input ports for the SFQ comparator unit. We successfully observe the transition curve of the probability of obtaining the signal from the SFQ coincidence circuit by sweeping photon arrival time to each SSPD and confirm that this curve shifts temporally upon changing the bias current to the Josephson transmission line (JTL) in the SFQ circuit. A systematic investigation reveals that the relation between time delay and the bias current to JTL can be estimated. The full width half maximum timing jitter of the SFQ circuit is 1.1 ps, which is sufficiently low so that it does not influence the entire timing jitter of the coincidence photon counter.

Design for Testability of SFQ Circuits

Test point insertion and set/scan techniques for enhanced testability in superconductive single-flux-quantum (SFQ) logic are proposed here. Test point insertion reduces the overhead of a set/scan chain while maintaining most of the functionality. Multiple ways of replacing costly (in terms of the number of Josephson junctions) SFQ multiplexers with mergers and blocking gates are proposed. The multiplexer control signals are replaced with a gated clock signal or separate bias networks for both functional and test paths. Clocked blocking gates or current-controlled Josephson transmission line segments are used to disable undesired data inputs. The clocked blocking gates for test point insertion in a 64-bit register requires 35% fewer Josephson junctions as compared to multiplexers. This advantage further increases for current-controlled blocking gates. Set/scan chain and test point insertion techniques are applied to several SFQ circuits to evaluate error characteristics and to provide built-in self-test of SFQ-compatible memory systems.

Circuit Description and Design Flow of Superconducting SFQ Logic Circuits

Superconducting Single-Flux-Quantum (SFQ) devices have been paid much attention as alternative devices for digital circuits, because of their high switching speed and low power consumption. For large-scale circuit design, the role of computer-aided design environment is significant. As the characteristics of the SFQ devices are different from conventional devices, a new design environment is required. In this paper, we propose a new timing-aware circuit description method which can be used for SFQ circuit design. Based on the description and the dedicated algorithms we have been developing for SFQ logic circuit design, we propose an integrated design flow for SFQ logic circuits. We have designed a circuit using our developed design tools along with the design flow and demonstrated the correct operation. key words: single-flux-quantum circuit, design methodology, circuit description, logic design, layout design, design verification

Improvement of Operating Margin of SFQ Circuits by Controlling Dependence of Signal Propagation Time on Bias Voltage

Superconductive single flux quantum (SFQ) digital circuits can operate at a clock frequency of several tens of gigahertz. However, the operating margin of these circuits decreases with an increase in the operating frequency because a timing error occurs in the low bias region. In this study, a novel design method that enables a wide operating margin at a high operating frequency has been investigated. The proposed circuits incorporate an additional bias feeding line in addition to the conventional bias feeding lines of the conventional Josephson transmission lines (JTLs) and can control the dependence of signal propagation time on the bias voltage. We have shown experimentally that in our proposed JTLs, the signal propagation time becomes more sensitive to the bias voltage. Timing errors can be avoided by inserting proposed JTL cells in the critical data path of the SFQ digital circuits. Circuit simulation results indicate that the operating margin of a bit-serial SFQ full adder, designed assuming the 2.5 kA/cm2 Nb process, can be improved by 15% compared with the conventional design at a frequency of 20 GHz by employing our novel design method.

Design and testing of high-speed interconnects for superconducting multi-chip modules

Superconducting single flux quantum (SFQ) circuits can process information at extremely high speeds, in the range of hundreds of GHz. SFQ circuits are based on Josephson junction cells for switching logic and ballistic transmission for transferring SFQ pulses. Multi-chip modules (MCMs) are often used to implement larger complex designs, which cannot be fit onto a single chip. We have optimized the design of wideband interconnects for transferring signals and SFQ pulses between chips in flip-chip MCMs and evaluated the importance of several design parameters such as the geometry of bump pads on chips, length of passive microstrip lines (MSLs) and number of corners in MSLs as well as flux trapping and fabrication effects on the operating margins of the MCMs. Several test circuits have been designed to evaluate the above mentioned features and fabricated in the framework of a 4.5 kA cm−2 HYPRES process. The MCM bumps for electrical connections have been deposited using a wafer-level electroplating process. We have found that, at the optimized configuration, the maximum operating frequency of the MCM test circuit, a ring oscillator with chip-to-chip connections, approaches 100 GHz and is not noticeably affected by the presence of MCM interconnects, decreasing by only about 3% with respect to the same circuit with no inter-chip connections.

Superconductive combinational logic circuit using magnetically coupled SQUID array

In this paper, we propose the development of superconductive combinational logic circuits. One of the difficulties in designing superconductive single-flux-quantum (SFQ) digital circuits can be attributed to the fundamental nature of the SFQ circuits, in which all logic gates have latching functions and are based on sequential logic. The design of ultralow-power superconductive digital circuits can be facilitated by the development of superconductive combinational logic circuits in which the output is a function of only the present input. This is because superconductive combinational logic circuits do not require determination of the timing adjustment and clocking scheme. Moreover, semiconductor design tools can be used to design digital circuits because CMOS logic gates are based on combinational logic. The proposed superconductive combinational logic circuits comprise a magnetically coupled SQUID array. By adjusting the circuit parameters and coupling strengths between neighboring SQUIDs, fundamental combinational logic gates, including the AND, OR, and NOT gates, can be built. We have verified the accuracy of the operations of the fundamental logic gates by analog circuit simulations.

1550 nm band optical input module with superconducting single-flux-quantum circuit

We developed an optical input module with a superconducting single-flux-quantum (SFQ) circuit for application of ultrafast photonic networks in the near future. The optical input module, consisting of a built-in photodiode (PD) with a coplanar waveguide transmission line, was fabricated on an InP substrate and flip-chip bonded with the SFQ circuit on a Si substrate. The fabricated PD showed photosensitivities of more than 0.2 A/W for the wavelength range 1480 to 1530 nm at 4.2 K. SFQ pulses were generated by less than 1 mW optical pulse input.

A single flux quantum circuit with a ferromagnet-based Josephsonπ-junction

We report on the functionality of a Nb-based superconducting singleflux quantum (SFQ) toggle flip-flop (TFF) circuit, comprising acomplementary superconductor–ferromagnet–superconductor (SFS) Josephsonπ-junction. The SFS junction was used as a phase shifting element inserted in the storage loop of theTFF. The fabricated circuits demonstrated correct functionality with the operation parameter ranges of ± 20%. The applicationof SFS π-junctions makes the SFQ circuits very compact, may substantially improve theirstability, and may also be suitable for integration with Josephson quantum circuits(qubits).

Comparisons of Synchronous-Clocking SFQ Adders

Recent advances of superconducting single-flux-quantum (SFQ) circuit technology make it attractive to investigate computing systems using SFQ circuits, where arithmetic circuits play important roles. In order to develop excellent SFQ arithmetic circuits, we have to design or select their underlying algorithms, called hardware algorithms, from different point of view than CMOS circuits, because SFQ circuits work by pulse logic while CMOS circuits work by level logic. In this paper, we compare implementations of hardware algorithms for addition by synchronous-clocking SFQ circuits. We show that a set of individual bit-serial adders and Kogge-Stone adder are superior to others.

Superconductive Random Number Generator Using Thermal Noises in SFQ Circuits

A novel high-speed physical random number generator using the superconductive single-flux-quantum (SFQ) circuits and thermal noises in the circuit has been proposed. The proposed physical random number generator is similar to an SFQ balanced comparator. Thermal noises in shunt resisters are used to obtain random outputs. Because of the high-sensitivity of SFQ circuits, the true random numbers can be generated without amplification of the noises at high clock frequency. Generation of the true random numbers at the frequency of several tens GHz can be realized by using the proposed circuit. Moreover, the circuit scale of the proposed circuit is very small and the generation frequency of the random number generator can be easily enhanced by parallelizing the circuits. We have designed and tested the superconductive physical random number generator using the 2.5 kA/cm2 Nb standard process and evaluated the quality of the generated random number train. We have examined a 220-bit random number train generated at a low frequency and no periodicity is observed. We believe that the superconductive physical random number generator can be applied to cryptographic applications for more secure information processing.

Development of Cryopackaging and I/O Technologies for High-Speed Superconductive Digital Systems

A cryocooled system with I/O interface circuits, which enables high-speed system operation of superconductive single-flux-quantum (SFQ) circuits at over 40GHz, and the demonstration of a 47-Gbps SFQ 2×2 switch system are presented. The cryocooled system has 32 I/Os and cools an SFQ multi-chip module (MCM) to 4K with a two-stage 1W Gifford-McMahon cryocooler. An SFQ 4:1 multiplexer (MUX) and an SFQ 1:4 demultiplexer (DEMUX) have been designed to interface the speed gap between the I/O (-10Gbps/ch) and SFQ circuits (>40GHz). An SFQ 2×2 switch chip, in which the MUX/DEMUX and an SFQ 2×2 switch are integrated, and an 8-channel superconductive voltage driver (SVD) chip have been designed with an advanced cell library for a junction critical current density of 10kA/cm2. An SFQ 2×2 switch MCM has been made by flip-chip bonding the switch chip and SVD chip on a superconductive MCM carrier with ∅50-μm InSn solder bumps. An SFQ 2×2 switch system, which is the switch MCM packaged in the cryocooled system, has been demonstrated up to a port speed of 47Gbps for the first time.

Single Flux Quantum Circuit and Packaging Technology for Sub-Kelvin Temperature Operation

Superconducting single flux quantum (SFQ) technology is well known for digital logic operations below 4.2 K, which are compatible with the Josephson junction qubit. Operation speed and signal sensitivity of circuits in SFQ are also sufficient to control qubits. Therefore, the SFQ circuit is a candidate technology for multiple qubit control. However, the self-heating effect of the SFQ circuit is a potential barrier to development of an SFQ-supported multiple qubit system because the qubit operating temperature is lower than the conventional 4.2 K. The multi-chip approach is a possible solution because the qubit chip can be thermally isolated from the SFQ circuitry. We report on recent progress in SFQ circuit and packaging technology for operation at sub-Kelvin temperatures. As for multi-chip module technology, a test sample of the multi-chip module shows good reliability of electrical connections between chips, and each solder bump has a bandwidth wide enough for signal transmission. We have designed lower power SFQ circuits for sub-Kelvin temperatures. The critical currents of Josephson junctions were scaled down, inductances were scaled up, and bias voltage was reduced to make power consumption lower. Based on our fabrication technology, critical current densities were optimized by considering trade-off relations between fabrication availability and operation speed. We successfully confirmed its correct operations at around 0.35 K. The combination of the multi-chip module and optimized SFQ circuits is very effective way of controlling qubit.