Super Steep Subthreshold Slope Research Articles

Analysis of Super-Steep Subthreshold Slope Body-Tied SOI MOSFET and its Possibility for Ultralow Voltage Application

Analysis of Super-Steep Subthreshold Slope Body-Tied SOI MOSFET and its Possibility for Ultralow Voltage Application

Characterization of Hysteresis in SOI-Based Super-Steep Subthreshold Slope FETs

Characterization of Hysteresis in SOI-Based Super-Steep Subthreshold Slope FETs

P-Channel and N-Channel Super-Steep Subthreshold Slope PN-Body Tied SOI-FET for Ultralow Power CMOS

In this paper, n-channel and p-channel super-steep subthreshold slope (SS) PN-body tied (PNBT) silicon on insulator field-effect transistors (SOI-FETs) are demonstrated. The PNBT structure has a symmetrical source and drain structure. The devices show super-steep SS (< 1 mV/dec) characteristics while maintaining low off current (< 1 pA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$ </tex-math></inline-formula> m) and high on/off ratio (up to 6 decades) with low drain voltage (Vd = ± 0.1 V), good output characteristics, and threshold voltage controllability. The devices have a body current and a hysteresis characteristic; however, these can be suppressed under proper device conditions. The operation mechanism of the PNBT SOI-FET is clarified by simulation, and an inherent thyristor on the PNBT structure plays a significant role. Both the p-channel and n-channel PNBT SOI-FET characteristics are discussed, and it is indicated that an ultralow power complementary metal-oxide-semiconductor can be realized by the PNBT SOI-FET.

Diode Characteristics of a Super-Steep Subthreshold Slope PN-Body Tied SOI-FET for Energy Harvesting Applications

In this paper, the diode characteristics of our newly proposed super-steep subthreshold slope “PN-body tied (PNBT) silicon-on-insulator field-effect transistor” are presented, and compared with conventional diodes. We report that the device possesses super-steep characteristics, low leakage current, and sharp turn-on characteristics, even in the ultralow voltage range (50 mV). These indicate that the PNBT diode can potentially be used in high-efficiency rectification for energy harvesting, particularly in situations where there is ultralow input power. In addition, the hysteresis characteristics and the slight shift of the voltage at zero current are confirmed as specific characteristics of PNBT diodes.

A Novel SuperSteep Subthreshold Slope Dual-Channel FET Utilizing a Gate-Controlled Thyristor Mode-Induced Positive Feedback Current

For the first time, we experimentally demonstrate an FET with a polycrystalline silicon (poly-Si) device featuring supersteep subthreshold slope (SS) around 20 mV/decade at room temperature. This novel dual-channel device is a three-wordline (WL) transistor fabricated in a poly-Si channel, with p+ source and n+ drain. The outer two WLs serve as the pass gates that control the virtual junction of the center WL device (main gate). Whether n-channel or p-channel characteristics are achieved depend on the bias polarity applied to the pass gates. Both read modes exhibit supersteep SS behavior for the center main gate. Theoretical analysis suggests that this three-WL FET device creates a gate-controlled thyristor mode, where a positive feedback current is induced when the center main gate voltage is above the onset value to induce the turned-on thyristor. Different from the usual tunneling FET (with reverse-biased junction bias), the p+/n+ junction is forward biased, and thus, the read current can approach $10~\mu \text{A}$ even for a narrow-width (~32 nm) poly-Si thin-film transistor, amounting to 0.3-mA/ $\mu \text{m}$ drive current. This device displays no hysteresis between forward and reverse voltage sweeping, and the steep SS has weak temperature/size dependence.

Negative Capacitance for Boosting Tunnel FET performance

We have proposed and investigated a super steep subthreshold slope transistor by introducing negative capacitance of a ferroelectric HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate insulator to a vertical tunnel FET for energy efficient computing. The channel structure and gate insulator are systematically designed to maximize the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratio. The simulation study reveals that the electric field at the tunnel junction can be effectively enhanced by potential amplification due to the negative capacitance. The enhanced electric field increases the band-to-band tunneling rate and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratio, which results in 10× higher energy efficiency than in tunnel FET.

Charge‐plasma‐based super‐steep negative capacitance junctionless tunnel field effect transistor: design and performance

A double-gate charge-plasma-based super-steep negative capacitance junctionless tunnel field effect transistor (NC-JLTFET) using a ferroelectric gate stack is proposed. Structurally, the NC-JLTFET consists of a heavily doped n-type silicon (Si) channel with two distinctive gates (control gate and fixed source gate). The fixed source gate accounts for the charge-plasma (hole plasma) formation which results in surrogate p-type doping by using work-function engineering. It induces a uniform p-region on the source side on the n-type doped Si film having a thickness less than the Debye length (L D). The key attribute of the NC-JLTFET is the ferroelectric gate stack which is employed as a control gate resulting in NC behaviour due to positive feedback among the electric dipoles in the ferroelectric material. The NC-JLTFET endeavours to achieve a super-steep sub-threshold slope, a paramount boost in drive current and a substantial enhancement in peak transconductance (g m) than the JLTFET. Meanwhile, it embraces the inherent advantages of the charge-plasma junctionless structure. Thus, it avails itself of a simple fabrication process flow and high immunity against process variations and random dopant fluctuations.

Complementary Germanium Electron–Hole Bilayer Tunnel FET for Sub-0.5-V Operation

In this letter, we present a novel device, the germanium electron-hole (EH) bilayer tunnel field-effect transistor, which exploits carrier tunneling through a bias-induced EH bilayer. The proposed architecture provides a quasi-ideal alignment between the tunneling path and the electric field controlled by the gate. The device principle and performances are studied by 2-D numerical simulations. This device allows interesting features in terms of low operating voltage (<; 0.5 V), due to its super-steep subthreshold slope (SSAVG ~ 13 mV/dec over six decades of current), ION/IOFF ratio of ~ 109, and drive current of ION ~ 10 μA/μm at VDD = 0.5 V. The same structure with symmetric voltages can be used to achieve a p-type device with ION and IOFF levels comparable to the n-type, which enables a straightforward implementation of complementary logic that could theoretically reach a maximum operating frequency of 1.39 GHz when VDD = 0.25 V.