Superjunction Layer Research Articles

Novel Si/SiC heterojunction lateral double-diffused metal oxide semiconductor field effect transistor with low specific on-resistance by super junction layer

A novel Si/SiC heterojunction lateral double-diffused metal oxide semiconductor (LDMOS) field effect transistor with the low specific on-resistance (Ron,sp) by super-junction (SJ) layer (Si/SiC SJ-LDMOS) is proposed in this paper. On the basis of using N-Buffer layer to solve substrate assisted depletion effect (SAD), breakdown point transfer terminal technology (BPT) is realized by the deep drain structure of Si/SiC heterojunction and electric field modulation is carried out, which further improves the breakdown voltage (BV) of Si/SiC SJ-LDMOS, alleviates the contradictory relationship between the BV and the Ron,sp. Through ISE TCAD simulation, the result shows that with the same drift region length of 20 μm, the BV is increased from 114 V of conventional SJ-LDMOS (Cov. SJ-LDMOS) and 270 V of SJ-LDMOS with N-Buffer layer (Buffer SJ-LDMOS) to 374 V of Si/SiC SJ-LDMOS, increased by 228% and 38%, respectively. In addition, the Ron,sp of Cov. SJ-LDMOS, Buffer SJ-LDMOS and Si/SiC SJ-LDMOS are 46.26 mΩ cm2, 26.96 mΩ cm2 and 25.85 mΩ cm2, respectively. Moreover, the figure-of-merit (FOM) of proposed Si/SiC SJ-LDMOS device is 5.411 MW/cm2, which means the Si/SiC SJ-LDMOS has a better performance to break the silicon limit. The influence of design parameters on device performance is also discussed.

4H-SiC Drift Step Recovery Diode with Super Junction for Hard Recovery.

Silicon carbide (SiC) drift step recovery diode (DSRD) is a kind of opening-type pulsed power device with wide bandgap material. The super junction (SJ) structure is introduced in the SiC DSRD for the first time in this paper, in order to increase the hardness of the recovery process, and improve the blocking capability at the same time. The device model of the SJ SiC DSRD is established and its breakdown principle is verified. The effects of various structure parameters including the concentration, the thickness, and the width of the SJ layer on the electrical characteristics of the SJ SiC DSRD are discussed. The characteristics of the SJ SiC DSRD and the conventional SiC DSRD are compared. The results show that the breakdown voltage of the SJ SiC DSRD is 28% higher than that of the conventional SiC DSRD, and the dv/dt output by the circuit based on SJ SiC DSRD is 31% higher than that of conventional SiC DSRD. It is verified that the SJ SiC DSRD can achieve higher voltage, higher cut-off current and harder recovery characteristics than the conventional SiC DSRD, so as to output a higher dv/dt voltage on the load.

A Lateral Double-Diffusion Metal Oxide Semiconductor Device with a Gradient Charge Compensation Layer

In order to better shield the substrate-assisted depletion (SAD) effect and improve the breakdown voltage of super-junction (SJ) devices, an SJ lateral double-diffusion metal oxide semiconductor device with a gradient charge compensation layer (gradient device) is proposed. The main feature of this structure is to introduce a gradient charge compensation layer between the SJ layer of a conventional device and the substrate. The depth of the gradient charge compensation layer increases gradually from the source to the drain. The charge distribution in the drift region is optimized by reducing the compensation charge on the side near the source and increasing the compensation charge on the side near the drain. Introduction of the layer improves shielding of the SAD effect, and the electric field on the surface of the structure is an approximately rectangular distribution, thus the breakdown voltage is improved. The simulation results show that the gradient device has 409-V breakdown voltage and a 9.5-MW cm−2 figure of merit with a drift region length of 21 μm. Compared with the conventional SJ structure (conventional device) with the same drift length, the breakdown voltage and figure of merit of the gradient device are increased by 57.3% and 137.5%, respectively.

A Simulation Study of a Novel Superjunction MOSFET Embedded With an Ultrasoft Reverse-Recovery Body Diode

In this paper, a novel superjunction (SJ) MOSFET embedded with an ultrasoft reverse-recovery body diode is proposed and studied by simulation. The device has a composite assistant layer, which consists of a highly doped n-buffer region and an extended p-pillar region, under the SJ layer. The assistant layer provides residual carriers during the reverse-recovery procedure and smoothens the current. Simulated results show that the soft factor is upgraded from 0.04 to over 0.3 when the depth of the assistant layer increases from $0~\mu \text{m}$ to that of the SJ layer. The increment of the specific ON-resistance is less than 10% if the concentration of the n-buffer region is 25 fold that of the n-pillar region.

Novel Superjunction LDMOS With a High-K Dielectric Trench by TCAD Simulation Study

A novel superjunction (SJ) lateral double-diffused MOSFET (LDMOS) with a deep High-K(HK) dielectric trench (HK SJ-LDMOS) is proposed and its mechanism is investigated by Technology Computer Aided Design (TCAD) simulations. The HK dielectric trench is embedded under the n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> drain, which is connected with the drain electrode. In the OFF-state, the reshaping effect of HK trench enhances the bulk electric field strength and weakens the peak electric field around the edge of the drain diffusion, which increases the breakdown voltage (BV). Moreover, because of the assistant depletion effect by the HK trench, a lower resistivity substrate is allowed for HK SJ-LDMOS, which also increases the doping concentration of the ntype buffer layer under the SJ layer of HK SJ-LDMOS, correspondingly. Thus, a lower specific ON-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> ) is also obtained. Simulation results show that the BV increases by 35.2% in comparison with the conventional buffered SJ-LDMOS with the same drift length. Moreover, HK SJ-LDMOS presents an excellent figure of merit, which is two times higher than that of the conventional buffered SJ-LDMOS.

A novel superjunction lateral double-diffused MOS with segmented buried P-layer

A novel superjunction (SJ) lateral double-diffused MOS (LDMOS) with charge compensation to obtain an ultralow specific on-resistance (Ron,sp) is proposed in this paper. Segmented Buried P-layer(SBP)SJ LDMOS introduces segmented buried P-layer between the drift region and the substrate. The buried layer with gradual length from the source to the drain of SBP SJ LDMOS can also optimize the charge distribution of the drift region, which means it will reduce the charge compensation for SJ layer caused by the drift region under the source and increase the charge compensation for SJ layer caused by the drift region under the drain, thus achieving charge balance in the SJ layer. Compared with the conventional(Con.) SJ LDMOS at the same drift region of 33.5 μm, the breakdown voltage (BV) of the SBP SJ LDMOS is 680.5 V, enhanced by 41.7%. In addition, P-layer can also assist in depleting drift region to increase the concentrate of drift region and to decrease the Ron,sp of the device. When the gate voltage is 15 V, the Ron,sp is 42.8 mΩ cm2, reduced by 20.5% and the figure-of-merit(FOM) is 10.8 MW cm−2, increased by 152.8%.

New super junction lateral double-diffused metal-oxide-semiconductor field-effect transistor with the P covered layer

In order to design the lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOS) with low loss required for a power integrated circuit, a new super junction LDMOS with the P covered layer which is based on the existing N buffered super junction LDMOS is proposed in this paper for the first time. The key feature of the proposed structure is that the P-type covered layer is partly above the N-type of the super junction layer, which is different from the N buffered super junction LDMOS. In this structure, the specific on-resistance of the device is reduced by using the high doped super junction layer; the problem of the substrate-assisted depletion which is produced due to the P-type substrate of the N-channel super junction LDMOS is eliminated by completely compensating for the charges of the N-type buffered layer and the P-type covered layer, thus improving the breakdown voltage. The charges of the N-type and P-type pillars are depleted completely. A new transmission path at the on-state is formed by N buffered layer to reduce the specific on-resistance, which is similar to the N buffered super junction LDMOS. However, the effect of N-type buffered layer of N buffered super junction LDMOS is not fully used. The drift region of the device is further optimized by the proposed device to reduce the specific on-resistance. The charge concentration of the N-type buffered layer in the proposed device is improved by the effect of charge compensation of the P covered layer. It is clear that high breakdown voltage and low specific on-resistance are realized in the proposed device by introducing the P-type covered layer and the N-type buffered layer. The results of the 3 D-ISE software suggest that when the drift region is on a scale of 10 μm, a specific on-resistance of 4.26 mΩ·cm2 obtained from P covered super junction LDMOS by introducing P covered layer and N buffered layer is reduced by about 59% compared with that of conventional super junction LDMOS which is 10.47 mΩ·cm2, and reduced by about 43% compared with that of N Buffered super junction LDMOS which is 7.46 mΩ·cm2.

A 700- V Junction-Isolated Triple RESURF LDMOS With N-Type Top Layer

A junction-isolated triple RESURF (JITR) LDMOS with high breakdown voltage (BV) and low specific on-resistance (R on,sp ) is proposed in this letter. Compared with the conventional triple RESURF (CTR) LDMOS, the new structure features a highly doped n-type top (N-top) layer at the surface of N-well, providing a low on-resistance surface conduction path in the on-state. The experimental result demonstrates that low R on,sp and high BV of above 730 V are achieved by the JITR LDMOS. R on,sp of the JITR LDMOS is about 15%-24.3% lower than that of the CTR LDMOS. The JITR LDMOS with horizontal N-top layer and P-buried layer resembles a super junction (SJ) LDMOS. Compared with the reported SJ LDMOS, the SJ layer of JITR LDMOS is formed in the longitudinal direction instead of the width direction, and the proposed JITR LDMOS exhibits almost the highest BV and high power figure of merit (FOM, defined as BV 2 /R on,sp ) in comparison to the published SJ LDMOS.

Low specific on-resistance power MOSFET with a surface improved super-junction layer

A novel low specific on-resistance (Ron,sp) integrable power metal-oxide-semiconductor field-effect transistor (MOSFET) with a surface improved super-junction (SISJ) layer is proposed. A super-junction layer is implemented at the surface of the drift region and the P pillar in super-junction layer is split into two parts with different doping concentrations. Firstly, the super-junction layer causes the multiple-direction depletion effect. The drift region doping concentration of the SISJ LDMOS is therefore increased significantly. Secondly, the super-junction layer provides a surface low on-resistance path. Thirdly, the new electric field peak introduced by the variation in the doping concentration of the P pillar modulates the surface electric field distribution, resulting in an improved breakdown voltage (BV). It reduces the device pitch for a specific BV capacity. All of them decrease Ron,sp sharply. The SISJ LDMOS exhibits a Ron,sp of 10.2mΩcm2 for BV=230V and decreases Ron,sp by 37% compared with a conventional lateral double-diffused MOSFET (LDMOS) at the same BV. Finally, because of the shallow depth of the SISJ layer, the proposed structure can be compatible with CMOS technology. Consequently, the SISJ LDMOS must be a competitive power device for power integrated circuit applications.

Low on-resistance high-voltage lateral double-diffused metal oxide semiconductor with a buried improved super-junction layer

A novel low specific on-resistance (Ron,sp) lateral double-diffused metal oxide semiconductor (LDMOS) with a buried improved super-junction (BISJ) layer is proposed. A super-junction layer is buried in the drift region and the P pillar is split into two parts with different doping concentrations. Firstly, the buried super-junction layer causes the multiple-direction assisted depletion effect. The drift region doping concentration of the BISJ LDMOS is therefore much higher than that of the conventional LDMOS. Secondly, the buried super-junction layer provides a bulk low on-resistance path. Both of them reduce Ron,sp greatly. Thirdly, the electric field modulation effect of the new electric field peak introduced by the step doped P pillar improves the breakdown voltage (BV). The BISJ LDMOS exhibits a BV of 300 V and Ron,sp of 8.08 mΩ·cm2 which increases BV by 35% and reduces Ron,sp by 60% compared with those of a conventional LDMOS with a drift length of 15 μm, respectively.

New Superjunction LDMOS With $N$-Type Charges' Compensation Layer

A new superjunction lateral double diffused MOSFET (LDMOST) is designed with an <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> -type buried layer in the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> -substrate near the drain to suppress the effect of substrate-assisted depletion resulting from <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> -type charges' compensating charges' imbalance between the pillars of the superjunction layer. By the effect of the electric field modulation, a more uniform surface electric field is obtained by the new high electric field peak introduced by the p-n junction of the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> -substrate and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> -type charges' compensation layer. The new effect of reduced bulk field is introduced to improve the vertical breakdown voltage (BV) by reducing the high bulk electric field around the drain. Fabricated <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> -buried SJ LDMOST with a drift region length of 35 mum and a pillar width of 4.0 mum exhibits a specific on resistance of 98 mOmegamiddotcm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a BV of 410 V.