Sum-product Decoding Research Articles

A study on acceleration of SP decoder using reliability of recording sequence by neural network based on parity check result in SMR system

We study signal processing methods to realize ultra-high-density hard disk drives (HDDs). Among them, we have applied the neural network to improve decoding performance in low-density parity-check (LDPC) coding and iterative decoding in the shingled magnetic recording (SMR) system. In this study, we realize acceleration of the sum-product (SP) decoding by updating the decoding reliability of the SP decoding using the reliability of the recording sequence calculated by the neural network based on the parity check results. As a result, the proposed system achieved error-free with the fewest number of iterations in the SP decoder compared to our previous studies.

A Study on Accelerating SP Decoding by Neural Network in SMR System

We have previously studied low-density parity-check (LDPC) coding and iterative decoding in the shingled magnetic recording (SMR) system as a signal processing method to realize ultra-high-density hard disk drives (HDD). In addition, we have proposed the application of the neural network to improve decoding performance and realize the automation of iterative decoding. In this study, we apply a neural network to accelerate iterative decoding in the sum-product (SP) decoder. As the result, the SP decoder with the neural network realized ”no errors” at the fewest times of the iterative decoding compared to our previous studies.

Concatenated Permutation Codes under Chebyshev Distance

Permutation codes are error-correcting codes over symmetric groups. We focus on permutation codes under Chebyshev (ℓ∞) distance. A permutation code invented by Kløve et al. is of length n, size 2n-d and, minimum distance d. We denote the code by φn,d. This code is the largest known code of length n and minimum Chebyshev distance d > n/2 so far, to the best of the authors knowledge. They also devised efficient encoding and hard-decision decoding (HDD) algorithms that outperform the bounded distance decoding. In this paper, we derive a tight upper bound of decoding error probability of HDD. By factor graph formalization, we derive an efficient maximum a-posterior probability decoding algorithm for φn,d. We explore concatenating permutation codes of φn,d=0 with binary outer codes for more robust error correction. A naturally induced pseudo distance over binary outer codes successfully characterizes Chebyshev distance of concatenated permutation codes. Using this distance, we upper-bound the minimum Chebyshev distance of concatenated codes. We discover how to concatenate binary linear codes to achieve the upper bound. We derive the distance distribution of concatenated permutation codes with random outer codes. We demonstrate that the sum-product decoding performance of concatenated codes with outer low-density parity-check codes outperforms conventional schemes.

A Study on Performance Evaluation With Neural Network Detector in SMR System

We previously applied a neural network detector (NND) to the low-density parity-check (LDPC) coding and iterative decoding system in a shingled magnetic recording (SMR) system. In this study, we evaluate the performance of iterative decoding using a new NND by computer simulation. The conventional NND gets the log-likelihood ratio (LLR) as the reliability of the sequence recorded from the two-dimensional finite impulse response (TD-FIR) filter output and the sum-product (SP) decoder output, but the new NND finds the LLR by adding the SP decoder input in order to consider the difference between the SP decoder input and the decoding result. Furthermore, we clarify that the new NND brings the almost same effect as the a posteriori probability (APP) decoder in the iterative decoding system.

Reliability Ratio Weighted Bit Flipping– Sum Product Algorithm for Regular LDPC Codes

In this work, we introduce a novel decoding algorithm named “Reliability Ratio Weighted Bit Flipping–Sum Product” (RRWBFSP) is proposed for regular LDPC codes. “Sum Product” [4] and “Reliability Ratio Weighted Bit Flipping” [6] are two separate methods that are combined in the new algorithm. The simulations show novel algorithm to exceed Sum-Product decoding algorithms by 0.34 dB. In addition, when compared to the Sum-Product, the RRWBFSP approach has about the same computational complexity. Thus, LDPC codes, of which the “Double-Orthogonal Convolutional Recursive” (RCDO) subfamily is envisioned for use in electronic hard disks and mobile terminals, can be easily iteratively decoded. This would have the impact of prolonging the life of the batteries and consequently reducing the ecological footprint of the discarded batteries.

An FPGA-Based LDPC Decoder With Ultra-Long Codes for Continuous-Variable Quantum Key Distribution

In this paper, we propose a good decoding performance, low-complexity, and high-speed decoder architecture for ultra-long quasi-cyclic LDPC codes by using the layered sum-product decoding scheme. To reduce implementation complexity and hardware resource consumption, the messages in the iteration process are uniformly quantified and the function Ψ(x) is approximated with second-order functions. The decoder architecture improves the decoding throughput by using partial parallel and pipeline structures. A modified construction method of parity check matrices was applied to prevent read&write conflicts and achieve high-speed pipeline structure. The simulation results show that our decoder architecture has good performance at signal-to-noise ratios (SNRs) as low as -0.6 dB. We have implemented our decoder architecture on a Virtex-7 XC7VX690T field programmable gate array (FPGA) device. The implementation results show that the FPGA-based LDPC decoder can achieve throughputs of 108.64 Mb/s and 70.32 Mb/s at SNR of 1.0 dB when the code length is 262,144 and 349,952, respectively. The decoder can find useful applications in those scenarios that require very low SNRs and high throughputs, such as the information reconciliation of continuous-variable quantum key distribution.

Parallel Genetic Algorithm Decoder Scheme Based on DP-LDPC Codes for Industrial IoT Scenarios

The new concept of Industry 4.0 has been developed: it includes both Internet of Things (IoT) structure and the local networks that are still needed to carry out real-time tasks. Genetic algorithms are successfully used for decoding some classes of error correcting codes, and offer very good performances when solving large optimization problems. This article proposes a decoder based on parallel Genetic Algorithms (PGAD) for Decoding Low Density Parity Check (LDPC) codes. The proposed algorithm gives large gains over the Sum-Product decoder, which proves its efficiency, the best performances are obtained for Ring Crossover (RC) as a type of crossover and the tournament as a type of selection. Furthermore, the performances of the new decoder are improved using Multi-criteria method. For the LDPC code, simulation results showed that our Proposed PGAD exceeds the sum-product by a gain of 1.5 dB at BER = 10-4, and the PGAWS exceeds the sum-product by 2.5 dB.

High Throughput and Resource Efficient Pipelined Decoder Designs for Projective Geometry LDPC Codes

Projective geometry (PG) based low-density parity-check (LDPC) decoder design using iterative sum-product decoding algorithm (SPA) is a big challenge due to higher interconnection and computational complexity, and larger memory requirement caused by relatively higher node degrees. PG-LDPC codes using SPA exhibits the best error performance and faster convergence. This paper presents an efficient novel decoding method, modified SPA (MSPA) that not only shortens the critical-path delay but also improves the hardware utilization and throughput of the decoder while maintaining the error performance of SPA. Three fully-parallel LDPC decoder designs based on PG structure, PG(2,GF( 2s )) of LDPC codes are introduced. These designs differ in their bit-node (BN) and check-node (CN) architectures. Fixed-point, 9-bit quantization scheme is used to achieve better error performance. Another significant contribution of this work is the pipelining of the proposed decoder architectures to further enhance the overall throughput. These parallel and pipelined designs are implemented for 73-bit (rate 0.616) and 1057-bit (rate 0.769) regular-structured PG-LDPC codes, on Xilinx Virtex-6 LX760 FPGA and on 0.18 μm CMOS technology for ASIC. Synthesis and simulation results have shown the better performance, throughput and effectiveness of the proposed designs.

A Study on Block-Based Neural Network Equalization in TDMR System With LDPC Coding

To achieve a high track density, two-dimensional magnetic recording (TDMR) is combined with shingled magnetic recording (SMR). SMR makes it possible to record 1 bit on a few grains. However, the performance will be remarkably deteriorated by the increased media noise, the inter-track and inter-symbol interference (ITI and ISI). Therefore, the application of effective equalization and error control coding are required. In this paper, we investigate a simple block-based neural network equalizer (NNE) that mitigates the influence of ITI and ISI. We compare the equalization effects of the NNE and a conventional 2-D equalizer with low-density parity-check (LDPC) coding based on a random Voronoi grain media model. Simulation results show the proposed block-based NNE achieves better bit error rate performance than the conventional 2-D linear equalizer followed by the a posteriori probability (APP) detector and a sum-product (SP) decoder. In addition, we find the block-based NNE is sensitive to write errors.

More Accurate Analysis of Sum-Product Decoding of LDPC Codes Using a Gaussian Approximation

This letter presents a more accurate mathematical analysis, with respect to the one performed in Chung et al.'s 2001 paper, of belief-propagation decoding for low-density parity-check (LDPC) codes on memoryless binary input-additive white Gaussian noise channels, when considering a Gaussian approximation (GA) for message densities under density evolution. The recurrent sequence, defined in Chung et al.'s 2001 paper, describing the message passing between variable and check nodes follows from the GA approach and involves the function φ(x), therein defined, and its inverse. The analysis of this function is here resumed and studied in depth to obtain tighter upper and lower bounds on it. Moreover, unlike the upper bound given in the above cited paper, the tighter upper bound on φ(x) is invertible. This allows a more accurate evaluation of the asymptotical performance of sum-product decoding of LDPC codes when a GA is assumed.

A Study on Iterative Decoding With LLR Modulator by Parity Check Information in SMR System

In recent years, shingled magnetic recording (SMR) has attracted attention as a new recording system of the hard disk drives. Although SMR can realize narrow track by overwriting data track like tile roofing, it has remarkable performance deterioration due to the influence of inter-track interference. Therefore, the performance improvement of the low-density parity-check (LDPC) coding and iterative decoding system using the sum-product decoding is required. In this paper, we propose the LDPC encoding and iterative decoding system with the log-likelihood ratio modulator and show the error floor is eliminated and improvement of signal-to-noise ratio to achieve the error free is obtained in the SMR under an areal recording density of 4 Tbits/in2 specification for the channel bit sequence coded by run-length limited and LDPC encoders by computer simulation. Therefore, the channel bit is composed bit about five magnetic grains.

Low‐complexity bound on irregular LDPC belief‐propagation decoding thresholds using a Gaussian approximation

Since irregular low-density parity-check (LDPC) codes are known to perform better than regular ones, and to exhibit, like them, the so-called ‘threshold phenomenon’, this Letter investigates a low-complexity upper bound on belief-propagation decoding thresholds for this class of codes on memoryless binary input additive white Gaussian noise channels, with sum-product decoding. A simplified analysis of the belief-propagation decoding algorithm is used, i.e. consider a Gaussian approximation for message densities under density evolution, and a simple algorithmic method, defined recently, to estimate the decoding thresholds for regular and irregular LDPC codes.

Joint Channel Estimation and LDPC Decoding Over Time-Varying Impulsive Noise Channels

This paper tackles the problem of channel estimation and decoding in environments that exhibit time-varying block-memoryless impulsive noise. In order to perform the estimation in continuous value space and the decoding in discrete value space jointly, a novel message passing framework is proposed that combines the sampling-importance resampling (SIR) estimator and the LDPC sum-product decoder in an iterative manner. The resampling process within the framework is further improved based on the asymptotic performance analysis for mismatched decoding. The simulation results prove the validity of the enhanced SIR estimator in the proposed method and demonstrate our method can achieve better performance than the LDPC decoder with quantile estimator.

Modified majority logic decoding of Reed–Muller codes using factor graphs

This study investigates the decoding algorithms of binary Reed-Muller (RM) codes. The main goal of the study is to modify majority-logic decoding using sum-product or min-sum decoding algorithms at the highest-order information bits in RM codes. Numerical results show that compared with the traditional majority-logic decoding algorithm, the modified majority-logic decoding method proposed in this study can reduce the bit error rate by a large margin. This is achieved without incurring a significant increase in decoding complexity because soft-decision decoding is only used in the highest information bits in RM codes whereas majority-logic decoding is still applied at the other orders of information bits in RM codes.

Design of Quasi-Cyclic Low Density Parity Check Decoder Using Optimized Min-Sum Algorithm

Low-density parity-check (LDPC) have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost , time, power and bandwidth requirements of target applications.
 Quasi-cyclic low-density parity-check (QC-LDPC) codes are an important subclass of LDPC codes that are known as one of the most effective error controlling methods. Quasi cyclic codes are known to possess some degree of regularity. Many important communication standards such as DVB-S2 and 802.16e use these codes.
 The proposed Optimized Min-Sum decoding algorithm performs very close to the Sum-Product decoding while preserving the main features of the Min-Sum decoding, that is low complexity and independence with respect to noise variance estimation errors.Proposed decoder is well matched for VLSI implementation and will be implemented on Xilinx FPGA family

Design of Channel Coded Heterogeneous Modulation Physical Layer Network Coding

In a two-way relay channel network (TWRC), the integration of channel coding into symmetric physical layer network coding (PNC) has been well studied, where both sources use exactly the same channel coding and modulation schemes and the relay decodes and reencodes the codewords obtained from the superimposed signals. How to integrate the channel coding into heterogeneous modulation PNC (HePNC), where the sources apply different modulations, is an open issue. In this paper, we propose a channel coded HePNC (CoHePNC) scheme under asymmetric TWRC. For repeat-accumulate (RA) codes applied at the sources, a full-state sum-product decoding algorithm is proposed which enables the relay to decode the superimposed signals from the sources to the raw decoding results firstly, and then re-encode and obtain the network-coded codewords by mapping the raw decoding results according to the proposed bit-level mapping functions. We further optimized the bit-level mapping functions according to the two source-relay channel conditions. Extensive simulation results demonstrated that the proposed CoHePNC outperforms the existing channel coded PNC schemes in terms of the relay decoding error rate and the end-to-end bit error rate under asymmetric TWRC scenarios.

Joint detection and decoding for physical‐layer network coding in power line channel

In this study, a joint detection and generalised sum-product decoding algorithm for a two-way relay physical-layer network coding (PLNC) system in power line communication is proposed. Distinct from the existing works which mainly focused on separate or iterative PLNC detection and decoding, the proposed algorithm is a belief propagation-based joint PLNC detection and decoding algorithm, which integrates the PLNC, symbol detector and channel decoder together. The proposed algorithm is described by a joint factor graph, in which the detection nodes are connected to the factor graph of a generalised sum-product decoder. The PLNC demodulation is redesigned to make sure that the degree of each detection node in the joint factor graph is more than one. A low computational complexity solution of the proposed joint decoding algorithm based on the majority-logic algorithm is also proposed. The simulation results reveal the validity of the proposed algorithms.

Analysis of LDPC code in the FH system with partial‐band interference

The performance of low-density parity-check (LDPC) code is analysed in the frequency hopping (FH) system with partial-band interference (PBI). Both of Slow Frequency hopping (SFH)/binary phase-shift keying (SK) and Fast Frequency hopping (FFH)/binary frequency-SK schemes are considered in which the channel fading and diversity combining are involved, respectively. The symmetry conditions on PBI channel are proven, and then the probability densities of initial message for sum–product decoder are derived. Given a probability of hopping to a jammed state, the decoding thresholds of LDPC codes on PBI channel are obtained using density evolution, which are in good agreement with the simulation results. Furthermore, the irregular LDPC codes are optimised over PBI channel, and the simulation result shows that it has better anti-jamming performance than the existing regular and irregular codes which have been employed in FH systems.

Useful Mathematical Tools for Capacity Approaching Codes Design

Focus of this letter is the oldest class of codes that can approach the Shannon limit quite closely, i.e., low-density parity-check (LDPC) codes, and two mathematical tools that can make their design an easier job under appropriate assumptions. In particular, we present a simple algorithmic method to estimate the threshold for regular and irregular LDPC codes on memoryless binary-input continuous-output additive white Gaussian noise (AWGN) channels with sum-product decoding, and, to determine how close are the obtained thresholds to the theoretical maximum, i.e., to the Shannon limit, we give a simple and invertible expression of the AWGN channel capacity in the binary input-soft output case. For these codes, the thresholds are defined as the maximum noise level, such that an arbitrarily small bit-error probability can be achieved as the block length tends to infinity. We assume a Gaussian approximation for message densities under density evolution, a widely used simplification of the decoding algorithm.

A Relaxed Min-Sum LDPC Decoder With Simplified Check Nodes

This letter presents a heuristic technique for simplifying the parity-check node operation in a relaxed min-sum iterative decoder. The proposed decoder eliminates the second-minimum computation in check nodes, which allows broadcasting the same output to all neighboring variable nodes to alleviate routing problem in VLSI implementations of low-density parity check (LDPC) decoders. The second-minimum, when required, is emulated by adding an offset to the first-minimum. The proposed relaxed decoder also uses a relaxation factor equal to 0.5 to simplify variable nodes. Simulation results for two LDPC codes show the proposed decoding algorithm with only 4-bit quantization closely matches the performance of floating-point normalized/offset min-sum and sum-product decoders in the waterfall region.