Sum Of Absolute Difference Architecture Research Articles

Analysis of Pel Decimation and Technology Choices to Reduce Energy on SAD Calculation

As the number of pixels per frame tends to increase in new high definition video coding standards such as HEVC and VP9, pel decimation appears as a viable means of increasing the energy efficiency of Sum of Absolute Differences (SAD) calculation. First, we analyze the quality costs of pel decimation using a video coding software. Then we present and evaluate two VLSI architectures to compute the SAD of 4x4 pixel blocks: one that can be configured with 1:1, 2:1 or 4:1 sampling ratios and a non-configurable one, to serve as baseline in comparisons. The architectures were synthesized for 90nm, 65nm and 45nm standard cell libraries assuming both nominal and Low-Vdd/High-Vt (LH) cases for maximum and for a given target throughput. The impacts of both subsampling and LH on delay, power and energy efficiency are analyzed. In a total of 24 syntheses, the 45nm/LH configurable SAD architecture synthesis achieved the highest energy efficiency for target throughput when operating in pel decimation 4:1, spending only 2.05pJ for each 4×4 block. This corresponds to about 13.65 times less energy than the 90nm/nominal configurable architecture operating in full sampling mode and maximum throughput and about 14.77 times less than the 90nm/nominal non-configurable synthesis for target throughput. Aside the improvements achieved by using LH, pel decimation solely was responsible for energy reductions of 40% and 60% when choosing 2:1 and 4:1 subsampling ratios, respectively, in the configurable architecture. Finally, it is shown that the configurable architecture is more energy-efficient than the non-configurable one.

Exploring high-order adder compressors for power reduction in sum of absolute differences architectures for real-time UHD video encoding

The sum of absolute difference (SAD) calculation is one of the most computing-intensive operations in video encoders compatible with recent standards, such as high-efficiency video coding (HEVC). SAD hardware architectures employ an adder tree to accumulate the coefficients from the absolute difference between two video blocks. This paper employs high-order adder compressors (HOAC) structures into SAD hardware architectures to achieve ultra-high definition (UHD) encoding in real time, using block sizes compatible with HEVC. The proposed HOAC architectures are power-efficient and enable low-power SAD hardware accelerators. Our throughput analysis shows that the HOAC-based SAD hardware architecture is capable of encoding UHD 4K ( $$3840\times 2160$$ ) videos in real-time at 60 frames per second. The architectures were entirely designed as dedicated ASIC blocks and were synthesized to ST 65 nm CMOS standard cells. Synthesis results show that SAD architectures using 64-2, 32-2, 16-2 and 8-2 compressors built from 4-2 compressors are significantly more efficient in terms of circuit area and total power dissipation when compared with SAD architectures using conventional adders selected by a commercial logic synthesis tool.

Low Power Oriented Full Search Block Based Motion Estimation (LP-FSBME) Architecture Using Power Efficient Adder Compressor For H.265 Coding Techniques.

H.265 coding is known as HIGH efficiency video coding (HEVC). This is most successful video compression standard and extended from H.264/MPEG-4 advanced video coding (AVC) for same level of video quality. However, H.265 improved better video quality for same bit rate. In video coding, motion estimation (ME) is determined the motion vector from adjacent frames. Various algorithms have been introduced by many researchers to accomplish low power oriented ME. However, low power oriented full search block based motion estimation (LP-FSBME) algorithm gives accurate results. Architecture of sum of absolute difference (SAD) is used an adder tree to accumulate the processing elements. Power efficient 16:2 adder compressors in SAD architecture reduce the power dissipation rather than convention adders in SAD architecture. The hardware implementation of proposed method is done in Xilinx Virtex 7 FPGA XC7VX1140T device with speed grade 1 in Xilinx software version 14.5 tool, developed in Verilog Hardware Description Language (Verilog-HDL), and simulated in ISE simulator for tennis, BQ terrace and Kimono videos with the resolution of 1080x720 pixels with 30fps.

Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design

Sum of absolute differences (SAD) calculation is one of the most time-consuming operations of video encoders compatible with the high efficiency video coding standard. SAD hardware architectures employ an adder tree to accumulate the coefficients from absolute difference between two video blocks. This paper exploits different adder compressors structures into the SAD hardware architecture. The architectures were synthesized to 45-nm CMOS standard cells. Synthesis results show that SAD architecture using 8–2 compressor composed with 4–2 compressors and Kogge–Stone adder in the recombination line reduces power dissipation by 25.5% on average when compared with the SAD architecture using conventional adders from a state-of-the-art synthesis tool. Our throughput analysis shows that the designed SAD units are capable of encoding full HD ( $1920\times 1080$ ) videos in real time at 30 frames/s.

Pipelined Architecture for Motion Estimation in HEVC Video Coding

Background: High Efficiency Video Coding (HEVC) is the latest video coding standard for video coding. Motion estimation is one of important stages in video coding. In HEVC, the conventional macroblocks are replaced by coding tree units (CTU). Method/Statistical Analysis: The maximum block size is increased from 16×16 to 64×64 in HEVC makes motion estimation more complex. An efficient hardware architecture ha to be designed for real time implementation of motion estimation. In motion estimation, sum of absolute difference (SAD) is calculated between current block and reference blocks present in two different video frames and minimum of SAD gives motion vector of the block. Findings: This paper presents design of pipelined SAD architecture for efficient SAD calculations. The proposed design is used in diamond search algorithm to carry out the motion estimation for evaluating the performance of the design. The proposed architecture employs pipelining at 8×8 block. The proposed design is implemented in TSMC 90 nm technology and operates at maximum frequency of 486 MHz. Applications/Improvements: The design achieves 78% reduction in power compared to the previous design and around 50 % increase in operating frequency.

Efficient Comparator based Sum of Absolute Differences Architecture for Digital Image Processing Applications

prolific use of images & videos in portable devices, raised the need to develop the efficient architectures for the ever increasing demand of portability with low power and high performance quality metrics. However the images and videos are the information's to be stored, but there compression while storing is the important part. This paper introduces a basic hardware component for the compression architectures. Comparator augments as general purpose core to Sum of Absolute difference (SAD) architecture used for the object recognition, generation of disparity maps of the stereo images and for estimating the motion in videos. The Subtraction part of the comparator is optimized by providing the parallel computation in processing the 2's complement operation. Transistor stacking and Logic optimization concepts are utilized to reduce the leakage power of the comparator design. 4-bit wide Comparator with smallest of two binary numbers functionality is modeled using Verilog HDL and synthesized using Synopsys Design Compiler. The design was mapped to 65nm technological library node and results were benchmarked with respect to standard ASIC design methodology. The proposed architectures have resulted in reduced leakage power about 7- 42 % for different proposed architectures and enabled the different corners for analysis.

Power Efficient Sum of Absolute Difference Algorithms for video Compression

Video Compression (VC) is one of the resource hungry key element in video communication and is commonly achieved using Motion Estimation (ME). In this paper we proposed power efficient one bit full adder and one of the simple and easy metric called Sum of Absolute Difference (SAD) for estimating the motion vectors in motion estimation. SAD is primarily used to detect motion in the video sub system. Here we proposed power efficient 4X4 and 8X8 SAD architectures. The proposed 4X4 SAD proves that 29%, 63.23% and 61.31% improvement in leakage power, dynamic power and total power respectively as compared with existing 4X4 SAD. Similarly the proposed 8X8 SAD which proves that 57%, 46.16% and 46.78% improvement in Leakage Power (LP), Dynamic Power (DP) and Total Power (TP) respectively as compared with that of existing 8X8 SAD at the gate level. The designs are implemented in ASIC methodology using cadence tools. Keywords - SAD, ME, VC, CSA, DSP, LP, DP, TP, FPGA etc. I. INTRODUCTION Many recent multimedia applications of digital video systems such as video conferencing, video-on- demand, video-phone, distance learning and digital TV, object tracking and many more have become popular products because of their convenience. Such applications require video compression with ever higher compression ratios, better visual quality and high bandwidth. The high efficiency video compression commonly uses the efficient hardware architectures. In general the development of hardware architectures are designed to form the integrated circuits which allows parallel processing of data from various sub blocks of the architectures, however hardware architectures suffers from limitations such as algorithm flexibility due to timing dependencies, which arises from the dataflow of various blocks of the architecture. Thus the development of good architecture of video codec in integrated circuits is very important. The customization of video codec is the video compression in the modern state of the art real time Digital Signal Processing (DSP) systems. Video compression is one of the techniques in video processing system to reduce resource usage. The two primary challenges addressed during video compression are:  Limited Network bandwidth.  Limited Storage capacity. Hence the two important metrics of a video encoder are low computational complexity & low power hardware implementation. Present day world, compression ratio plays the major role in the field of video processing. The motion in the video scene will reduce the efficiency of the compression ratio. Hence the motion estimation field has seen the highest research topic and interested issue in the past a few decades. In short the motion estimation means the estimation of the displacement (or velocity) of image structures from one frame to another in a time sequence of 2-D images of the video in order to achieve video compression in video coding. The efficiency of the compression ratio can be increased by exploiting the similarities between the video frames. The simple metric system is the SAD algorithm, where the absolute differences between the corresponding elements are added up. There are varieties of video coding standards in the video processing systems; the modern video coding standard is H.264/AVC. This coding standard uses the Variable Block Size Motion Estimation (VBSME), in this standard; the computation requirements are much higher than the previous coding standards such as H.263/ MPEG-IV. In H.264/AVC, each picture frame is divided into many macro blocks.

A High-Performance Low Cost SAD Architecture for Video Coding

This paper presents a high-performance low cost sum of absolute difference (SAD) architecture for motion estimation, which consumes a lot of computation and resource in video coding. Unlike many hardware implementations based on complement adders, this paper features the comparison of unsigned numbers to generate partial results of SAD and determine minimum SAD. Furthermore, the compression array unit is implemented by 4-2 compressor. This general-purpose architecture is implemented with a 2-stage pipeline and it is suitable for block-based video compression standards, such as MPEG-4, H.263 and H.264/AVC. Performance analysis shows that compared with other SAD architectures, the proposed architecture reduces 15.3%-22.9% area at almost no cost of latency.

A High-Performance Sum of Absolute Difference Implementation for Motion Estimation

This paper presents a high-performance sum of absolute difference (SAD) architecture for motion estimation, which is the most time-consuming and compute-intensive part of video coding. The proposed architecture contains novel and efficient optimizations to overcome bottlenecks discovered in existing approaches. In addition, designed sophisticated control logic with multiple early termination mechanisms further enhance execution speed and make the architecture suitable for general-purpose usage. Hence, the proposed architecture is not restricted to a single block-matching algorithm in motion estimation, but a wide range of algorithms is supported. The proposed SAD architecture outperforms contemporary architectures in terms of execution speed and area efficiency. The proposed architecture with three pipeline stages, synthesized to a 0.18-mum CMOS technology, can attain 770-MHz operating frequency at a cost of less than 5600 gates. Correspondingly, performance metrics for the proposed low-latency 2-stage architecture are 730 MHz and 7500 gates