Successive Approximation Register Research Articles

A Review on Fundamentals of Noise-Shaping SAR ADCs and Design Considerations

A general overview of Noise-Shaping Successive Approximation Register (SAR) analog-to-digital converters is provided, encompassing the fundamentals, operational principles, and key architectures of Noise-Shaping SAR (NS SAR). Key challenges, including inherent errors in processing circuits, are examined, along with current advancements in architecture design. Various issues, such as loop filter optimization, implementation methods, and DAC network element mismatches, are explored, along with considerations for voltage converter performance. The design of dynamic comparators is examined, highlighting their critical role in the SAR ADC architecture. Various architectures of dynamic comparators are extensively explored, including optimization techniques, performance considerations, and emerging trends. Finally, emerging trends and future challenges in the field are discussed.

A First-Order Noise-Shaping SAR ADC with PVT-Insensitive Closed-Loop Dynamic Amplifier and Two CDACs

This paper presents a first-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, (supply) voltage, and temperature (PVT)-insensitive closed-loop integrator and data-weighted averaging (DWA). The use of a cascode floating inverter amplifier (FIA)-type dynamic amplifier with high gain enables an aggressive noise transfer function while minimizing the power consumption associated with the use of an active filter. In the proposed ADC, the residue is generated by a capacitive digital-to-analog converter (CDAC) employing DWA, which is made possible by employing a second CDAC, which operates after the SAR operation is completed. The proposed ADC is designed with a 28 nm CMOS process with 1 V power supply. The simulation results show that the ADC achieves the SNDR of 71.2 dB and power consumption of 228 μW when operated with a sampling rate of 80 MS/s and oversampling ratio (OSR) of 10. The Schreier figure-of-merit (FoM) is 173.6 dB, and Walden FoM is 9.6 fJ/conversion-step.

An Energy-Efficient 12-Bit VCO-Based Incremental Zoom ADC with Fast Phase-Alignment Scheme for Multi-Channel Biomedical Applications

This paper presents a low-power, energy-efficient, 12-bit incremental zoom analog-to-digital converter (ADC) for multi-channel bio-signal acquisitions. The ADC consists of a 7-stage ring voltage-controlled oscillator (VCO)-based incremental ΔΣ modulator (I-ΔΣM) and an 8-bit successive approximation register (SAR) ADC. The proposed VCO-based I-ΔΣM can provide fast phase-alignment of the ring-VCO to reduce the interval settling time; thereby, the I-ΔΣM can accommodate time-division-multiplexed input signals without phase leakage between consecutive measurements. The SAR ADC also adopts splitting unit capacitors that can support VCM-free tri-level switching and prevent invalid states from the phase frequency detector with minimal logic gates and switches. The proposed ADC has been fabricated in a standard 180 nm standard 1P6M CMOS process, exhibiting a 67-dB peak signal-to-noise ratio, a 74-dB dynamic range, and a Walden figure of merit of 19.12 fJ/c-s, while consuming a power of 3.51 μW with a sampling rate of 100 kS/s.

Energy‐efficient switching method using input‐swapping for high‐resolution successive approximation register analog‐to‐digital converters

AbstractThis paper presents an energy‐efficient digital‐to‐analog converter (DAC) switching method with low common‐mode variations for high‐resolution successive approximation register (SAR) analog‐to‐digital converters (ADCs), while enabling to implement resolutions such as 14‐bit as compared to the typical 10‐bit. The proposed switching method enables high resolution by having a nearly constant common‐mode voltage and employing input‐swapping to use the reference voltage (Vref) only in the sampling phase. This method eliminates the need for the third reference voltage during the entire DAC switching steps, which reduces the required number of switches at the bottom plates of the capacitors. The use of lower number of switches not only lowers the DAC control logic complexity, but also results in a faster operation, lower power, and smaller area. When compared to conventional 10‐bit SAR ADCs, the proposed switching method in a 10‐bit implementation reduces the average energy and area by 96.09% and 75%, respectively, while offering high‐resolution implementation options such as 14 bits.

Flexible and fully integrated 4-bit SAR ADC using metal-oxide TFTs

This paper presents a flexible fully integrated 4-bit successive approximation register (SAR) analog-to-digital converter (ADC), which is fabricated by unipolar n-type indium-zinc-oxide thin-film transistors. A bootstrap switch and a comparator with a pre-amplifier are proposed and employed to realize the SAR ADC. The fabricated SAR ADC achieves a sampling rate of up to 20 kHz and a peak signal-to-noise and distortion ratio of 22.9 dB, corresponding to an effective-number-of-bits of 3.52 bits. The static performance of −0.58/+0.37 LSB DNL and −0.49/+0.39 LSB INL is achieved.

Multi-laser source interference suppression using the time-coding method for SPAD-based flash DToF systems

Flash-type direct time-of-flight (DToF) image sensors use an in-pixel successive approximation register time-to-digital converter (SAR TDC) for time quantization. However, in a scene where multiple DToF systems exist simultaneously, different laser signals from multiple sources will produce mutual signal interference between DToF systems, causing the DToF system’s incorrect measurement. In this paper, we present a method called time coding, which inserts delay time bins between different working periods to suppress the interference laser together with the SAR TDC. The time-coding method is designed using a 110 nm complementary metal oxide semiconductor (CMOS) technology and verified by behavioral model and circuit simulation. Regardless of traditional systems or systems equipped with time coding, DToF systems with certain patterns of time coding can reduce interference noise by at least 95%, maintaining a measurement accuracy of 99% or higher at long distances.

A bridged‐switch energy‐efficient switching scheme for SAR ADCs with 2× input range

AbstractIn recent years, successive approximation register (SAR) analogue‐to‐digital converters (ADCs) have been widely applied in Internet of Things (IoT) sensor devices. To reduce the power consumption of ADCs, a bridged‐switch energy‐efficient switching scheme for SAR ADCs with a 2× input range is proposed. Due to the use of top‐plate sampling, overall shift and bridged switch, the energy consumption of the first three comparisons and reset is zero, meanwhile the energy consumption of the fifth comparison is greatly reduced. The proposed switching scheme has an average energy consumption of 13.084CVref2, which reduces the switching energy by 99.04% compared to the conventional switching scheme. The proposed switching scheme can achieve a 2× input range with the same supply voltage, effectively reducing ADC power consumption and making it more suitable for IoT applications.

A 96 dB DR Second-Order CIFF Delta-Sigma Modulator with Rail-to-Rail Input Voltage Range

A second-order delta-sigma modulator (DSM) is proposed for readout integrated circuits of sensor applications requiring a small area and low-power consumption. The proposed second-order CIFF DSM with the architecture of cascaded-of-integrator feedforward (CIFF) basically consists of two integrators, a 3-bit quantizer, data-weighted averaging (DWA) circuit, and clock generator. The use of the 3-bit quantizer instead of the single-bit quantizer reduces the size of the feedback capacitor in the first integrator. The 3-bit quantizer is designed based on a successive approximation register analog-to-digital converter for small area and low power implementation. Furthermore, the proposed second-order CIFF DSM has a single supply without an additional reference driver while having a wide analog input voltage range with rail to rail. The proposed second-order CIFF DSM, implemented using a 130 nm 1-poly 6-metal CMOS process with a supply of 1.5 V, has an area of 0.096 mm2. It has a sampling frequency of 500 kHz for the implementation of an input bandwidth of 2 kHz and an oversampling ratio of 125. The measured peak signal-to-noise and distortion ratio is approximately 90 dB when the differential analog input signal has a frequency of 353 Hz and an amplitude of 1.2 Vpp. The measured dynamic range is approximately 96.3 dB.

High-Speed 16-Bit SAR-ADC Design at 500 MS/s with Variable Body Biasing for Sub-Threshold Leakage Reduction

In this study, a high-performance 16-bit, 500 MS/s successive approximation register analog-to-digital con-verter (SAR-ADC) with variable body biasing (VBB) for re-ducing sub-threshold leakage is designed and optimized. The suggested ADC architecture makes use of a voltage threshold complementary metal-oxide-semiconductor (VTCMOS) cir-cuit with Widlar current mirror technology to efficiently con-sume 39.2 μW at an operating voltage of 1.0 V. Notably, the optimized ADC achieves outstanding performance measures, such as a signal-to-noise and distortion ratio (SNDR) of 97 dB and a total harmonic distortion (THD) of -97.97 dB, which are crucial markers of the ADC's accuracy and fidelity. An over-view of the growing need for high-resolution ADCs in contem-porary high-speed data conversion systems opens the study. The main goal of this effort is to improve overall ADC per-formance and tackle the problem of sub-threshold leakage. The Widlar current mirror technology and the VTCMOS cir-cuit are integrated for enhanced linearity, decreased current mismatch errors, and minimized leakage current. This inte-gration is highlighted in the full explanation of the ADC de-sign. The advent of the VBB approach as a successful method of leakage reduction is a significant contribution to this re-search. The theoretical foundations and workings of the VBB technique are discussed, and thorough simulations and tests are used to assess how the VBB technique affects leakage cur-rent and circuit performance. The SAR-ADC design and simulations were carried out using Cadence Virtuoso soft-ware.

Test and performance of the CMS ECAL barrel data conversion and digital processing ASIC for HL-LHC

In preparation for the high luminosity upgrade of the Large Hadron Collider, a new data conversion and digital processing ASIC, called LiTE-DTU, was designed. Implemented in a 65 nm CMOS technology, the LiTE-DTU features two 12-bit 160 MS s-1 successive approximation register time-interleaved ADCs, a data processing unit and enables efficient data transmission at 1.28 Gbps.The LiTE-DTU has undergone extensive testing in both laboratory and beam tests, demonstrating excellent performance in the pre-production version, showing the production readiness of the design. The results of this comprehensive series of tests will be presented.

An evenly-spaced-phase all-digital DLL using dual-loop SAR control

This study introduces an all-digital delay-locked loop (ADDLL), which generates 20 evenly-spaced-phase clock signals. A successive-approximation register (SAR)-based dual-loop control is used to realize the locking process of the ADDLL. A modified SAR unit combined with a tri-state digital phase detector (TSDPD) is adopted to achieve a closed-loop operation of the ADDLL. A delay matrix, which can significantly reduce the jitter accumulation, is used to generate evenly spaced phases without using a long-cascaded delay line. Additional harmonic-lock detector circuits are added to the two control loops to avoid the harmonic lock issue. The ADDLL is designed and fabricated using a 0.18μm mixed-signal CMOS technology with an active area of 0.109 μm2. The lock range of the ADDLL is 30–230 MHz and the power consumption of the ADDLL is 8.9 mW at 100 MHz. The measured rms jitter is 23.3 ps at 100 MHz, and the results show a good linearity of the multiphase outputs at a 100 MHz input clock where the maximum DNL and INL are 0.08 and -0.22 LSB, respectively. The proposed ADDDLL is highly suitable for low-frequency, low-power, and high-time-resolution applications.

Design of a 16–bit 500 MS s–1 SAR-ADC at 45 nm for low power and high frequency applications

This study gives a thorough analysis of the performance of a 45 nm CMOS process-designed 16-bit 500 MS/s successive approximation register analog-to-digital converter (SAR-ADC). 16-bit R-2R DAC double-tail dynamic latch, Widlar current method, variable body-biasing technique, sample and hold block, 16-bit SAR, and 16-bit latch are used to design proposed SAR-ADC block. The SAR-ADC design and simulations were carried out using Cadence Virtuoso software. This powerful electronic design automation (EDA) tool facilitated the design, layout, and simulation of the ADC, ensuring a comprehensive analysis of its performance characteristics. MATLAB was used for post-simulation data analysis, processing, and visualization. The proposed SAR-ADC is compared with few existing examples listed as ADS8881, LTC2380–16, ADS8344, LTC2368, and MAX11156 on the performance metrics including signal-to-noise ratio (SNR), figure of merit (FOM), total harmonic distortion (THD), resolution, delay, power consumption and figure of Merit (FOM). This work is highlighting different aspects of the suggested architecture and demonstrates how it outperforms benchmark of ADCs in terms of power usage, SNR, THD, and FOM. A SAR-ADC attains a power consumption of 39.2 μW while operating at sampling frequency of 500 MS s–1 at supply voltage of 1 V. The results provide fresh perspectives for potential improvements in existing work in terms of reduction in power consumption and high-speed ADC at 16-bit resolution and also Jitter is scrutinized across various stages of the SAR-ADC. The proposed low power, high speed and high-resolution SAR ADC is targeted for high-quality analog-to-digital signal conversion useful in industrial automation systems, medical devices, IoT and audio processing modules.

A Tunable Foreground Self-Calibration Scheme for Split Successive-Approximation Register Analog-to-Digital Converter

The capacitor mismatch among diverse defects caused by variations in the manufacturing process significantly affects the linearity of the capacitor array used to implement the capacitive digital-to-analog converter (CDAC) in the successive-approximation register (SAR) analog-to-digital converter (ADC). Accordingly, the linearity of the SAR ADC is limited by that of capacitor array, resulting in serious yield loss. This paper proposes an efficient foreground self-calibration technique to enhance the linearity of the SAR ADCs by mitigating the capacitor mismatch based on the split ADC architecture along with variable capacitors. In this work, two ADC channels (i.e., ADC1 and ADC2) for the split ADC architecture include their capacitive DACs (CDACs) whose binary-weighted capacitor arrays consist of variable capacitors. A charge-sharing SAR ADC is used for each ADC channel. In the normal operation mode, their digital outputs are averaged to be the final ADC output, as in a conventional split ADC. In the calibration mode, every single binary-weighted capacitor for the two ADCs is sequentially calibrated by making parallel or/and antiparallel connection among two or thee capacitors from the two channels. For instance, because the capacitors of the CDACs ideally exhibit the binary-weighted relation as Cn=2×Cn−1, the variable capacitor Cn of ADC1 can be updated to be closest to the sum of Cn−1 of ADC1 and Cn−1 of ADC2 for the calibration. For the process, the two capacitor arrays of the two ADCs can be reconfigured to be connected to each other, so that the Cn of ADC1 can be connected with two of the Cn−1 of ADC1 and ADC2 in antiparallel. The two voltages at the top and the bottom plates of the CDAC are compared by a comparator of ADC1, and the comparison results are used to update Cn. This process is iterated, until Cn is in agreement with the sum of two of Cn−1. Finally, all the capacitors can be calibrated in this way to have the binary-weighted relation. The simulation results based on the proposed work with a split SAR ADC model verified that the proposed technique can be practically used, by showing that the total harmonic distortion and the signal-to-noise-and-distortion ratio were enhanced by 21.8 dB and 6.4 dB, respectively.

A Reconfigurable Hybrid ADC Using a Jump Search Algorithm

This paper presents a reconfigurable hybrid Analog to Digital Converter (ADC) designed specifically for bio-signal processing, aiming to achieve low power consumption and high area efficiency. The proposed ADC utilizes a combination of 10-bit Most Significant Bit (MSB) Successive Approximation Register (SAR) and 2–4-bit Least Significant Bit (LSB) Single Slope (SS) architectures. The SS architecture incorporates the Dummy Capacitor Quantization Method (DCQM) which employs a 10-bit MSB dummy capacitor. This dummy capacitor can be configured to represent the 2-LSBs or reconstruct 4-LSBs. The reconfigurability of the ADC is achieved through the control of the reset timing of a 5-bit counter enabled by an external signal. The proposed ADC was fabricated using a Complementary Metal Oxide Semiconductor (CMOS) n-well 1-poly 8-metal process. Experimental measurements revealed that the ADC operates at a speed of 454 kS/s with power consumption of 18.7 μW. The Effective Number of Bits (ENoB) achieved by the ADC is 10.9 bits based on a 14-bit scale or 10.2 bits based on a 12-bit scale. The Figure of Merit (FoM) for the ADC is calculated to be 21.5 fJ/step for the 14-bit scale and 22.1 fJ/step for the 12-bit scale.

A capacitive mismatch calibration method for SAR ADCs based on TDC

AbstractThe capacitance mismatch problem limits the accuracy improvement of high‐precision SAR ADCs (Successive Approximation Register Analog‐to‐Digital Converters). To address the capacitance array mismatch in SAR ADCs, this paper proposes a novel capacitor calibration scheme based on the Time‐to‐Digital Converter (TDC). This scheme achieves calibration accuracy as high as 0.01% and can be flexibly designed to meet the accuracy requirements of SAR ADCs. Simulation results indicate that the capacitance mismatch issue of a redundant capacitor 13‐bit SAR ADC can be completely eliminated, and the effective number of bits (ENOB) approach the ideal value of 13.18 bits. Additionally, the analog component of this scheme utilizes four inverter chains, two D flip‐flops, and four counters, without requiring a large area for auxiliary calibration capacitors.

A Highly Integrated Lab-on-a-CMOS Platform for Real-Time Monitoring of E. Coli Growth Kinetics.

Existing miniaturized and cost-effective solutions for bacterial growth monitoring usually require offline incubators with constant temperature to culture the bio-samples prior to measurement. Such a separated sample preparation and detection scheme requires extensive human intervention, risks contamination, and suffers from poor temporal resolution. To achieve integrated sample preparation and real-time bacterial growth monitoring, this article presents a lab-on-a-CMOS platform incorporates an optical sensor array, temperature sensor array, micro-heaters, and readout circuits. Escherichia coli's (E. coli) optimum growth temperature of 37 °C is achieved through a heat regulation system consisting of two micro-heaters and an on-chip temperature sensor array. A photodiode array with an in-pixel capacitive trans-impedance amplifier to reduce inter-pixel cross-coupling is designed to extract the optical information during bacterial growth. To balance the footprint, power consumption, and quantization speed, a 10 b column successive-approximation register (SAR)/single-slope (SS) dual-mode analog-to-digital converter (ADC) is designed to digitize the temperature and optical signals. Fabricated in a standard 0.18 um CMOS process, the proposed platform can regulate the sample temperature to 37 +/- 0.2/0.3 °C within 32 mins. Enabled by an on-chip heat regulation system and photodetectors, the prototype demonstrates a real-time monitoring of bacterial growth kinetics and antibiotic responses. Minute-level temporal resolution is achieved as this proposed platform is free of extensive and time-consuming human intervention. The proposed platform can be viably used in contamination sensitive applications such as antibiotic tests, stem cell cultures, and organ-on-chips.

A High ENOB 14-Bit ADC without Calibration

This paper presents an implementation of a 14-bit 2.5 MS/s differential Successive-Approximation-Register (SAR) analog-to-digital converter (ADC) to be used for sensing multiple analog input signals. A differential binary-weighted with split capacitance charge-redistribution capacitive digital-to-analog converter (CDAC) utilizing the conventional switching technique is designed, without using any calibration mechanism for fast power-on operation. The CDAC capacitor unit has been optimized for improved linearity without calibration technique. The SAR ADC has a differential input range 3.6 Vpp, with a SNDR of 80.45 dB, ENOB of 13.07, SFDR of 87.16 dB and dissipates an average power of 0.8 mW, while operating at 2.5 V/1 V for analog/digital power supply. The INL and DNL is +0.22/−0.34 LSB and +0.42/−0.3 LSB, respectively. A prototype ADC has been fabricated in a conventional CMOS 65 nm technology process.

Radiation Detector Front-End Readout Chip with Nonbinary Successive Approximation Register Analog-to-Digital Converter for Wearable Healthcare Monitoring Applications.

A 16-channel front-end readout chip for a radiation detector is designed for portable or wearable healthcare monitoring applications. The proposed chip reads the signal of the radiation detector and converts it into digital serial-out data by using a nonbinary successive approximation register (SAR) analog-to-digital converter (ADC) that has a 1-MS/s sampling rate and 10-b resolution. The minimum-to-maximum differential and integral nonlinearity are measured as -0.32 to 0.33 and -0.43 to 0.37 least significant bits, respectively. The signal-to-noise-and-distortion ratio and effective number of bits are 57.41 dB and 9.24 bits, respectively, for an input frequency of 500 kHz and a sampling rate of 1 MS/s. The SAR ADC has a 38.9-fJ/conversion step figure of merit at the sampling rate of 1 MS/s. The proposed chip can read input signals with peak currents ranging from 20 to 750 μA and convert the analog signal into a 10-bit serial-output digital signal. The input dynamic range is 2-75 pC. The resolution of the peak current is 208.3 nA. The chip, which has an area of 1.444 mm × 10.568 mm, is implemented using CMOS 0.18-μm 1P6M technology, and the power consumption of each channel is 19 mW. This design is suitable for wearable devices, especially biomedical devices.

A 78 dB 0.417 mW Second-Order NS SAR ADC with Dynamic Amplifier-Assisted Integrator

The noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) is an innovative hybrid structure that offers performance advantages. The NS-SAR ADC leverages the SAR ADC as its foundation and combines oversampling technology and noise-shaping technology found in Sigma-Delta ADC. This integration effectively combines the strengths of both structures and enhances overall performance. The ADC features a simple circuit structure, compact chip area, and high energy efficiency, which has positioned it as a prominent research area. In this paper, leveraging the TSMC 65 nm GP process, the NS-SAR ADC is designed with a power supply voltage of 1 V. This design adopts an 8-bit differential capacitor structure, operates at a sampling frequency of 16 MS/s, and achieves an oversampling rate of 16 times the desired performance indicators. Through extensive circuit post simulation verification, the SNR obtained reaches 78 dB, providing an effective bit resolution of 12.7 bits. The core chip area of the ADC measures 366 × 333 μm2, while the power consumption is impressively low at 417 μW and FoMs is 168 dB.

A 0.55-mm2 8-bit 32-GS/s TI-SAR ADC with optimized hierarchical sampling architecture

This paper analyzes the bandwidth of the time-interleaved analog-to-digital converter (TI-ADC) with hierarchical sampling and presents an 8-bit 32-GS/s TI-ADC in 28-nm CMOS. The front-end sampler is implemented by a two-stage hierarchical sampling architecture to extend the analog input bandwidth. The 32-way sub-ADCs are realized with 2b/cycle successive approximation register (SAR) architecture and non-binary search strategy, which meet the requirements of high speed, medium resolution, and strong robustness. Multi-phase low-jitter clock tree is designed based on the delay-locked loop (DLL). Calibration methods for timing skew, offset and gain mismatches are introduced to improve accuracy. The proposed TI-SAR ADC achieves an analog input bandwidth of 23.7 GHz. It occupies an active area of 0.55 mm2 and consumes 356 mW at 1.8/1 V supply.