This study aims to propose a gate structure of high k + SiO$_2$ for a fully depleted silicon-on-Insulator (FD-SOI) MOSFET. We developed a two-dimensional model to calculate its subthreshold surface potential of the front gate, threshold voltage, and drain induced barrier lowering (DIBL) effect. Based on the structure and different dielectric permittivity of FD-SOI MOSFET, the MOSFET of the subthreshold state is divided into several distinct rectangular equivalent sources. Furthermore, two-dimensional (2D) boundary value problems of Poisson and Laplace equations are built on the polygon region. Then, we use the method of separation of variables and the eigenfunction expansion to solve the 2D boundary value problems, and obtained their 2D solutions. Computational results show that the high k + SiO$_2$ gate can effectively suppress the degradation of FD-SOI MOSFET threshold voltage, the aggravation of DIBL effect, and the FIBL effect, which are caused by the dielectric permittivity of high k. Since the equations of the model are linear equations, their computational cost is minimal so that the model can be used for not only modeling and simulation of FD-SOI MOSFETs but also as a device model of circuit simulators.