Subthreshold MOSFETs Research Articles

Two-Stage OTA With All Subthreshold MOSFETs and Optimum GBW to DC-Current Ratio

An approach for the design of two-stage class-AB OTAs with sub- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1{\boldsymbol {\mu }}\text{A}$ </tex-math></inline-formula> current consumption is proposed and demonstrated. The approach employs MOS transistors operating in subthreshold and allows maximum gain-bandwidth product (GBW) to be achieved for a given DC current budget, by setting optimum distribution of DC currents in the two amplifier stages. Following this strategy, a class AB OTA was designed in a standard 0.5- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\boldsymbol {\mu }}\text{m}$ </tex-math></inline-formula> CMOS technology supplied from 1.6-V and experimentally tested. Measured GBW was 307 kHz with 980-nA DC current consumption while driving an output capacitance of 40 pF with an average slew rate of 96 V/ms.

0.13 μm Low-Power CMOS Current Starved VCO for Vibration Energy Harvesters

This work presents a current starved voltage-controlled oscillator (VCO) based on the standard 0.13- $\mu \text{m}$ CMOS process. Incorporated with the power management circuit (PMC), the current starved VCO generates an average periodic signal at a frequency of 84.81 kHz. In addition, to assure that the VCO has a stable periodic signal output regarding the varied control voltage, a voltage reference is realized. The proposed architecture makes full use of subthreshold and deep triode MOSFETs without any other components. A reference voltage of 258.35 mV is obtained in response to the supply voltage 1.0–3.2 V. The architecture exhibits a linear sensitivity of 0.49%/V at 27 °C. Power consumption of the proposed circuit is $3.546~\mu \text{W}$ at 3 V of the voltage supply. The output of the architecture leads to a time-control local oscillator, which can be employed in a PMC for vibration energy harvesters.

A Design Methodology Using the Inversion Coefficient for Low-Voltage Low-Power CMOS Voltage References

This paper presents an analog design methodology, which uses the selection of the inversion coefficient of MOS devices, to design low-voltage and low-power (LVLP) CMOS voltage references. The motivation of this work comes from the demand for analog design methods that optimize the sizing process of transistors working in subthreshold operation. The advantage of the presented method – compared to the traditional approaches for circuit design – is the reduction of design cycle time and the minimization of simulation iterations when the proposed equations are used. As a case study, a LVLP voltage reference based on subthreshold MOSFETs with a supply voltage of 0.7 V was designed in a 0.18-μm CMOS technology.

Design and Characterization of a 10 × 10 Pixel Array THz Camera in 350 nm CMOS Technology

In this paper, a $10\times 10$ pixel array camera for room-temperature THz imaging application in 350 nm CMOS technology is presented. The camera consists of a $10\times 10$ focal-plane array (FPA) of THz detectors, on-chip column amplifiers, digital-to-analog converter (DAC) and on-chip memory for per-pixel calibration. High performance THz detectors are realized by integrating on-chip antennas and sub-threshold Si MOSFETs. The detectors are biased with a current source for increased responsivity and improved NEP. Our designed detector improves responsivity and NEP by a factor of 900 and 7, respectively, compared to conventional photo-voltaic (cold) FET-based detector in the same technology node and detection settings. Additionally, we proposed a successive-approximation (SA) calibration scheme to adjust the operating point of the pixels to maximize the THz response and improve uniformity, in the presence of pixel-to-pixel process variation. At 200 GHz illunimation frequency, the average responsivity and NEP of the 2D imager are measured as 16.4 kV/W and $216~\frac {nW}{\sqrt {Hz}}$ , respectively, with an image acquisition rate of 2 Hz. The responsivity and NEP of a representative pixel are extrapolated to 10 KHz (where 1/f noise has substantially decreased) for comparison with literature. The extrapolated values are 19 kV/W and $535~\frac {pW}{\sqrt {Hz}}$ , respectively. By placing the THz camera in an optical setup, we were able to acquire images of concealed metal objects in a cardboard box at 200 GHz illumination frequency.

Design of High Power Supply Rejection Ratio Complementary Metal-Oxide-Semiconductor Bandgap Voltage Reference Using Single Node Approach

This paper describes a compact, low voltage and high power supply rejection ratio (PSRR) Bandgap voltage reference circuit by using subthreshold MOSFETs. The proposed reference circuit is implemented using 0.18 μm CMOS technology. The circuit simulation is performed using the Cadence Spectre and Synopsys Hspice. The circuit generates the mean output reference voltage of 164 mV and temperature coefficient of 15.5 ppm/°C when temperature is swept from –40 °C to 120 °C at power supply of 1.2 V. For better PSRR, a feed forward mechanism is used. The proposed design has only single transistor for start-up circuit. The measured settling time for output reference voltage is observed to be less than 4 μs. No filtering capacitor is used to improve the PSRR, which is –97 dB up to 1 MHz and subsequently reduces to –47.5 dB at 158 MHz.

A 0.5-V-supply, 37.8-nW, 17.6-ppm/°C switched-capacitor bandgap reference with second-order curvature compensation

This paper presents a switched-capacitor (SC) bandgap reference (BGR) with second-order curvature compensation for ultra-low power systems. The gate-source voltage of a sub-threshold MOSFET is proposed to implement the second-order curvature compensation voltage in this work. And then, a SC network is used, not only to add the second-order voltage and the first-order one together, but also to fulfill the summing weight effectively and precisely. In this way, the silicon area and power consumption can be reduced simultaneously. Furthermore, the design methodology of summing weight is investigated, and thus the temperature coefficient (TC) can be significantly reduced. The proposed SC-BGR was implemented and simulated in a CMOS 0.18 μm process, the average output voltage is 426.1 mV, achieving a TC of 17.6 ppm/°C from −20 to 100 °C under a 0.5 V minimum supply voltage. With the help of the SC architecture, a small chip area of 0.0975 mm2 is achieved with only 37.8-nW power consumption.

A 0.9-V 33.7-ppm/°C 85-nW Sub-Bandgap Voltage Reference Consisting of Subthreshold MOSFETs and Single BJT

A low temperature coefficient (TC) and high power supply ripple rejection (PSRR) CMOS sub-bandgap voltage reference (sub-BGR) circuit using subthreshold MOS transistors and a single BJT is presented in this brief. The proposed sub-BGR consists of a novel complementary-to-absolute-temperature (CTAT) voltage generator based on a scaled emitter-base voltage of a BJT, and an improved proportional-to-absolute-temperature (PTAT) voltage generator based on stacking of $\Delta V_{\mathbf {GS}}$ of sub- $V_{\mathbf {TH}}$ MOSFETs. As the CTAT circuit achieves a reduced absolute value of the negative TC, the PTAT circuit achieves reduced power consumption without consuming a large chip area. The proposed sub-BGR circuit is implemented in a standard 0.18- $\mu \text{m}$ CMOS process. Measured results show that the sub-BGR circuit can run with a supply voltage down to 0.9 V while the power consumption is only 85 nW. An average TC of 33.7 ppm/°C and a PSRR of better than −40 dB over the full frequency range are achieved.

Exponential‐to‐linear conversion for fluorescence lifetime measurement

A new scheme for CMOS-based fluorescence lifetime imaging with hardware-level exponential-to-linear conversion is proposed. The exponential relationship between drain current and drain-to-source voltage in a subthreshold MOSFET is explored for linearisation of the photocurrent generated during a fluorescence decay. Simple measurement of the resulting slope, either through voltage or time measurement, provides lifetime information in a single excitation cycle. The scheme is less sensitive to time and voltage errors compared with charge modulation techniques and are suitable for applications, where high-frame rate and rapid extraction are desired.

A 1.2 V, 3.0 ppm/°C, 3.6 μA CMOS bandgap reference with novel 3-order curvature compensation

This paper presents a bandgap reference with a high-order curvature compensation circuit which can improve the temperature coefficient (TC) in a wide temperature range. The proposed compensation circuit includes a second-order and a third-order curvature current generators as well as an I-V converter. These two curvature currents are achieved by utilizing the exponential behavior of sub-threshold MOSFET and used for compensating the high-order temperature dependence of BJT base-emitter voltage via I-V converter. The proposed BGR is implemented in a CMOS 0.18 μm process with the active area of 0.056 mm2. Measurements on ten samples showed that at the minimum supply voltage 1.2 V, the TC varies from 1.7 to 6.9 ppm/°C over a temperature range of 170 °C (−45 °C–125 °C) with an average value of 3.0 ppm/°C and the total current consumption of 3.6 μA at room temperature. In the supply voltage range of 1.2–1.8 V, the line regulation (LR) is 0.025%/V.

Designing an Inverter-based Operational Transconductance Amplifier-capacitor Filter with Low Power Consumption for Biomedical Applications

The operational transconductance amplifier-capacitor (OTA-C) filter is one of the best structures for implementing continuous-time filters. It is particularly important to design a universal OTA-C filter capable of generating the desired filter response via a single structure, thus reducing the filter circuit power consumption as well as noise and the occupied space on the electronic chip. In this study, an inverter-based universal OTA-C filter with very low power consumption and acceptable noise was designed with applications in bioelectric and biomedical equipment for recording biomedical signals. The very low power consumption of the proposed filter was achieved through introducing bias in subthreshold MOSFET transistors. The proposed filter is also capable of simultaneously receiving favorable low-, band-, and high-pass filter responses. The performance of the proposed filter was simulated and analyzed via HSPICE software (level 49) and 180 nm complementary metal-oxide-semiconductor technology. The rate of power consumption and noise obtained from simulations are 7.1 nW and 10.18 nA, respectively, so this filter has reduced noise as well as power consumption. The proposed universal OTA-C filter was designed based on the minimum number of transconductance blocks and an inverter circuit by three transconductance blocks (OTA).

A low-voltage, low-power voltage reference based on subthreshold MOSFETs

A novel low-voltage low-power CMOS voltage reference independent of temperature is presented in this design. After considering the combined effect of (1) a perfect suppression of the temperature dependence of mobility; (2) the compensation of the channel length modulation effect on the temperature coefficient, a temperature coefficient of 10 ppm/[Formula: see text]C is achieved. Moreover, by adopting the subthreshold MOSFETs, there are no resistors used in the proposed structure. Therefore, the maximum supply current measured at the maximum supply voltage is 70 nA and at 80[Formula: see text]C. The circuit can be used as a voltage reference for high performance and low power dissipation on a single chip.

A 3.9ppm/◦C 8.8nW and High PSRR Subthreshold CMOS Multiple Voltage Reference

A voltage reference with low Temperature coefficient (TC) and three outputs, which is compatible with high Power supply rejection ratio (PSRR) and low power consumption, is presented in this paper. The proposed reference circuit operating with all transistors biased in subthreshold region, provides three reference voltages of 340mV, 680mV, and 1020mV. Subthreshold MOSFET design allows the circuit to work with minimum current consumption of 7.4nA at the supply voltage 1.2V. The mean line sensitivity is 1.7%/V under a supply voltages ranging from 1.2 to 3V. The Power supply rejection ratio (PSRR) of 340mV output voltage simulated at 100Hz and 10MHz is over than 51.9dB and 120.4dB, respectively. Monte Carlo simulation shows a mean TC is 3.9ppm/ ◦ C with a standard deviation of 1ppm/ ◦ C over a set of 500 samples, in a temperature range from –30 ◦ C to 100 ◦ C. The active area of the presented voltage reference is 0.003mm2.

Design methodology for MOSFET-based voltage reference circuits implemented in 28 nm CMOS technology

This work presents a detailed methodology to design a precision voltage reference circuit using MOSFET devices. First, the I–V relations of saturation and subthreshold MOSFETs are presented along with the temperature dependency of these devices. Then, a step-by-step procedure on how to design the main building blocks of voltage reference circuits is discussed. The proper relations between these building blocks are detailed. Moreover, circuit techniques to minimize the impact of process, voltage and temperature (PVT) variations on the voltage reference circuit are introduced. In order to verify the methodological approach, a novel circuit is presented. This new design has been simulated in the state-of-the-art 28nm CMOS technology using Synopsys Custom Designer and HSPICE CAD tools. It generates a reference voltage of 252mV with line sensitivity (LS) of 0.64% in a supply voltage range of 0.85–4.1V. The temperature coefficient (TC) is 218.8ppm/°C, through a temperature range of −15–80°C. The power supply rejection ratio (PSRR) is −34dB at 50Hz and −48.6dB at 1MHz. Finally, the power consumption is 395nW at nominal supply voltage. The process variations coefficient is 0.19%, and the peak-to-peak output noise is 3.08μV/(Hz)1/2 at 10Hz.

A 0.7 V Relative Temperature Sensor With a Non-Calibrated &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$\pm 1~^{\circ}{\rm C}$&lt;/tex&gt;&lt;/formula&gt; 3&lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$\sigma$&lt;/tex&gt;&lt;/formula&gt; Relative Inaccuracy

This paper presents a new low-voltage relative temperature sensor for multi-core digital processor on-chip thermal management in a 180 nm CMOS process. Three types of sensing diodes including Schottky barrier diode (SBD), subthreshold MOSFET diode and dynamic threshold MOSFET (DTMOS) diode have been investigated for low-voltage operation, while traditional parasitic PNP-bipolar junction transistor (BJT) diodes are implemented to provide a performance reference. A matrix of 7 $\times$ 7 small remote sensor nodes is implemented on the chip with a deployment density of 49/0.81 ${\rm mm}^{2}$ and sharing the same bias current generator, control logic, and data converter. The measured minimum supply voltage (not including the clock control block) of the sensor is 0.7 V over $-55~^{\circ}{\rm C}$ to 125 $~^{\circ}{\rm C}$ . The relative sensing inaccuracies $(3\sigma)$ without calibration are less than $\pm 1.5~^{\circ}{\rm C}$ , $\pm 1.2~^{\circ}{\rm C}$ and $\pm 1~^{\circ}{\rm C}$ for the designs based on SBD, subthreshold MOSFET, and DTMOS, respectively. To the best of the authors’ knowledge, this is the first time that non-calibrated relative sensing accuracy is reported for SBD-based and DTMOS-based temperature sensors, and the best reported result for the design based on subthreshold MOSFET. The absolute inaccuracies with calibration-per-chip are also presented. Furthermore, the multi-location thermal monitoring function has been experimentally demonstrated and a 1.8 $^{\circ}{\rm C/mm}$ on-chip temperature gradient was detected.

Analysis and Comprehensive Analytical Modeling of Statistical Variations in Subthreshold MOSFET's High Frequency Characteristics

In this research, the analysis of statistical variations in subthreshold MOSFET's high frequency characteristics defined in terms of gate capacitance and transition frequency, have been shown and the resulting comprehensive analytical models of such variations in terms of their variances have been proposed. Major imperfection in the physical level properties including random dopant fluctuation and effects of variations in MOSFET's manufacturing process, have been taken into account in the proposed analysis and modeling. The up to dated comprehensive analytical model of statistical variation in MOSFET's parameter has been used as the basis of analysis and modeling. The resulting models have been found to be both analytic and comprehensive as they are the precise mathematical expressions in terms of physical level variables of MOSFET. Furthermore, they have been verified at the nanometer level by using 65~nm level BSIM4 based benchmarks and have been found to be very accurate with smaller than 5 % average percentages of errors. Hence, the performed analysis gives the resulting models which have been found to be the potential mathematical tool for the statistical and variability aware analysis and design of subthreshold MOSFET based VHF circuits, systems and applications.

A Subthreshold MOSFET Voltage Reference Based on Current Mirror Technology Under 55 nm CMOS Process

A Subthreshold MOSFET Voltage Reference Based on Current Mirror Technology Under 55 nm CMOS Process

Comprehensive Analytical Probabilistic Model of the Random Variation in Subthreshold MOSFET's High Frequency Performance

Comprehensive Analytical Probabilistic Model of the Random Variation in Subthreshold MOSFET's High Frequency Performance

Offset error reduction using gate‐bulk‐driven error correction amplifier for low‐voltage sub‐bandgap reference

Presented is a gain-boosted gate-bulk-driven error correction amplifier with reduced offset errors for low-voltage sub-bandgap reference designs. The method can be applied to sub-bandgap circuits with BJT diodes, subthreshold MOSFETs or Schottky barrier diodes. Detailed analysis and circuit implementation are presented. Low voltage operation has been verified over - 55 to 125 °C. Simulation and measurement results demonstrate the minimised offset error and improved supply sensitivity, which indicates the effectiveness of the proposed gain boosting mechanism.

A 0.003-mm2, 0.35-V, 82-pJ/conversion ultra-low power CMOS all digital temperature sensor for on-die thermal management

In this paper, a 0.35 V, 82 pJ/conversion ring oscillator based ultra-low power CMOS all digital temperature sensor is presented for on-die thermal management. We utilize subthreshold circuit operation to reduce power and adopt an all-digital architecture, consisting of only standard digital gates. Additionally, a linearization technique is proposed to correct the nonlinear characteristics of subthreshold MOSFETs. A bulk-driven 1-bit gated digitally controlled oscillator is designed for the temperature sensing node. Also, a 1-bit time-to-digital converter is employed in order to double the fine effective resolution of the sensor. The proposed digital temperature sensor has been designed in a 90-nm regular V T CMOS process. After a two-point calibration, the sensor has a maximum error of ?0.68 to +0.61 °C over the operating temperature range from 0 to 100 °C, while the effective resolution reaches 0.069 °C/LSB. Under a supply voltage of 0.35 V, the power dissipation is only 820 nW with the conversion rate of 10K samples/s at room temperature. Also, the sensor occupies a small area of 0.003 mm2.

A low-power biologically-inspired chaotic oscillator with process and temperature tolerance

This paper presents a low-power, biologically-inspired silicon neuron based implementation of a chaotic oscillator circuit. The silicon neuron structure is based on Hodgkin---Huxley neuron model. Subthreshold MOSFET and current reuse techniques have been utilized to achieve a low-power consumption of 180.30 nW for the room temperature (27 °C) and typical process corner. The chaotic behavior of the circuit is confirmed by calculating the largest Lyapunov exponent. A sensitivity analysis of the proposed chaotic oscillator shows that the circuit maintains the chaotic behavior for five different process corners within the temperature range of 0---60 °C.