Subthreshold Logic Gates Research Articles

Analytical subthreshold current model of the dual-material tri-gate (DMTG) MOSFET and its application for subthreshold logic gate

Multi-gate MOSFETs are considered for realizing ultra-low-power circuits due to their superior channel control capability and short channel effect (SCE) resistance. To achieve this goal, it is necessary to establish a suitable compact device circuit model for them. However, current research focuses more on single-material multi-gate MOSFET, and there is no research report on dual-material logic gates. In this work, we develop a subthreshold current model for dual-material tri-gate (DMTG) MOSFET. It is found that the gate metal close to the source can affect the subthreshold characteristics of the transistor to a greater extent. Moreover, combined with the equivalent transistor model, the noise margin (NM) model of the subthreshold inverter composed of DMTG MOSFETs is developed. The nearly equal NM can be obtained by equal NM design (END). An appropriate work function can be selected through END to obtain the optimal NM when designing the inverter. The NM under different device geometric parameters is given, and the simulation result shows that the model accuracy reaches 98%. Finally, the effect of DMTG structure on the device drain induced barrier lowering (DIBL) is given, which effectively reduces DIBL by 42%. These models still remain high accuracy when the device channel length shrink down to 20 nm, which provide the possibility for DMTG MOSFET to be effectively applied to ultra-low-power circuits.

Junctionless Multiple-Gate (JLMG) MOSFETs: A Unified Subthreshold Current Model to Assess Noise Margin of Subthreshold Logic Gate

With the quasi-3-D scaling equation, quasi-3-D minimum channel potential, and drift-diffusion model, a unified subthreshold current model for junctionless multiple-gate (JLMG) MOSFETs including quadruple-gate (QG), triple-gate (TG), and omega-gate ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega \text{G}$ </tex-math></inline-formula> ) devices is developed. With this subthreshold current model, the noise margin (NM) behavior of the subthreshold logic gate composed of JLMG MOSFETs is assessed. With the same cross-sectional area of the devices, the QG MOSFET provides the largest NM among the three devices due to its smallest scaling length. On the contrary, the TG MOSFET with the largest scaling length exhibits the smallest NM. The short-channel-degraded NM behavior can be similarly seen in these devices. In terms of design triangle (DT) of subthreshold logic gate, the QG MOSFET can provide the largest DT as opposed to the smallest one supplied by the TG device. The transistor strength balance (TSB) between p-type and n-type JLMG MOSFETs can be adjusted by tuning the gate work function to implement the optimum NM design. Finally, the impact of random doping fluctuation (RDF) on NM degradation is also discussed in this work.

Elliptical nanowire FET: Modeling the short-channel subthreshold current caused by interface-trapped-charge and its evaluation for subthreshold logic gate

Based on the quasi-3D potential approach, quasi-3D scaling theory, drift-diffusion model, and equivalent flat-band voltage shift, a short-channel subthreshold current caused by the interface-trapped-charge is modeled for the elliptical nanowire FET. With the subthreshold current, the logic swing (LS) of the subthreshold logic gate composed of elliptical nanowire FET is theoretically evaluated. It indicates that the positive interface-trapped-charge can degrade the high output voltage (V OH ) due to its increased/decreased the subthreshold current of N-FET/P-FET. However, the negative interface-trapped-charge can decrease/increase the subthreshold current of N-FET/P-FET, which hence deteriorates the low output voltage (V OL ). Both degradation of the subthreshold current and LS (i.e., ΔI sub and ΔLS) caused by short-channel effects (SCEs) can be well-controlled by the properly selected scaling factor of α. With the minimum scaling factor, the minimum LS degradation for the subthreshold logic gate can be uniquely determined. • Providing the robust interface-trapped-charged-degraded subthreshold model for the elliptical MOSFET. • Examining how the short-channel-effects together with the interface-trapped-charge-effects affect the logic swing of the subthreshold logic gate.

Nanosheet FET: A new subthreshold current model caused by interface-trapped-charge and its application for evaluation of subthreshold logic gate

Based on the quasi-3D potential approach, quasi-3D scaling theory, drift-diffusion model, and equivalent flat-band shift, a new subthreshold current model caused by the interface-trapped-charge is developed for the nanosheet FET. With the subthreshold current Isub, the noise margin (NM) of the subthreshold logic gate composed of nanosheet FET is thoroughly evaluated. It is found that the positive interface-trapped-charge can degrade the high noise margin (NMH) due to its increased/decreased subthreshold current of N-FET/P-FET. On the contrary, the negative interface-trapped-charge can decrease/increase subthreshold current of N-FET/P-FET, which hence deteriorates the low noise margin (NML). Both degradation of the subthreshold current and NM (i.e., ΔIsub and ΔNM) caused by short-channel effects (SCEs) can be well-controlled by the properly selected scaling factor of α. With the minimum scaling factor αmin that allows for the minimum noise margin degradation (ΔNM), the minimum channel length Lmin for the nanosheet FET can be obtained as it is readily applied for the subthreshold logic gate.

A New Device-Parameter-Oriented DC Power Model for Symmetric Operation of Junctionless Double-Gate &lt;sc&gt; mosfet&lt;/sc&gt; Working on Low-Power CMOS Subthreshold Logic Gates

Based on the subthreshold current and equivalent transistor models, a new device-parameter-oriented average DC power model average DC power (PDC) for symmetric operation of junctionless double-gate mosfet (JLDGFET) working on the low-power CMOS subthreshold logic gate is developed. Although short-channel effects can increase P DC significantly, the balanced transistor strength will reduce PDC more efficiently by improving the consistency of transistor strength between P-JLDGFET and N-JLDGFET. Being similar to DIBL, the minimum channel length that corresponds to the allowable maximum PDC in designing the low-power logic gate can be determined according to the scaling theory. Although the inverter (INV) may act as the fundamental building unit for the logic circuits due to its least gate counts among INV, nand , and nor , it consumes the most PDC among these logic gates. The minimum DC power PDC,min can be obtained by tuning the gate work-function, which ensures the equal transistor strength between P-JLDGFET and N-JLDGFET. Both of the variability and sensitivity induced by the process parameters are also accounted for in developing PDC model.

A New Device-Physics-Based Noise Margin/Logic Swing Model of Surrounding-Gate MOSFET Working on Subthreshold Logic Gate

In this paper, we present a device-physics-based noise margin (NM)/logic swing (LS) model of surrounding-gate (SRG) MOSFET working on subthreshold CMOS logic gates. Based on the device physics and equivalent transistor model, theoretical analysis of the main dc parameters, including LS and NM for SRG MOSFET operating in low-voltage condition, is revealed. It is shown that the device parameters, such as the thick silicon thickness $t_{\mathrm{ si}}$ , thick gate oxide thickness $t_{\mathrm{ ox}}$ , and short channel length $L_{g}$ , can severely degrade the LS and NM. On the contrary, both the small subthreshold slope $\eta $ and balanced transistor strength S induced by device parameters can suppress the NM and LS degradation efficiently. The required minimum supply voltage $V_{\mathrm{ dd,min}}$ for the subthreshold CMOS logic gate is derived by the criterion of the NM ≥ KT/ $q$ to ensure the correct logic gate operation. Being similar to DIBL, both NM and LS degraded by the device parameters can also be uniquely determined and controlled by the scaling factor according to scaling theory. Finally, considerations on the impact of process/voltage/temperature variation are also included for NM/LS behavior analysis.