Subthreshold Current Characteristics Research Articles

A Two-Dimensional Model for the Surface Potential and Subthreshold Current of Doped Double-Gate (DG) MOSFETs with a Vertical Gaussian-Like Doping Profile

An analytical two-dimensional (2D) model for the surface potential distribution and subthreshold current of the Double-Gate (DG) MOSFETs having Gaussian-like doping profile in the vertical direction of the silicon channel has been presented in this paper. The model is based on the solution of the 2D Poisson's equation in the fully depleted channel region using evanescent method. The effect of doping profile parameters on the surface potential has also been presented. The potential distribution function has been utilized to investigate the subthreshold current characteristics of the device. The validity of the proposed model is shown by comparing the analytical results with the simulation data obtained by the 2D device simulator ATLAS™. The proposed model is considered to be a very accurate and compact one since it does not include any fitting parameter.

A Novel Body-Tied Silicon-On-Insulator(SOI) n-channel Metal-Oxide-Semiconductor Field-Effect Transistor with Grounded Body Electrode

A novel body-tied silicon-on-insulator(SOI) n-channel metal-oxide-semiconductor field-effect transistor with grounded body electrode named GBSOI nMOSFET has been developed by wafer bonding and etch-back technology. It has no floating body effect such as kink phenomena on the drain current curves, single-transistor latch and drain current overshoot inherent in a normal SOI device with floating body. We have characterized the interface trap density, kink phenomena on the drain current () curves, substrate resistance effect on the curves, subthreshold current characteristics and single transistor latch of these transistors. We have confirmed that the GBSOI structure is suitable for high-speed and low-voltage VLSI circuits.

Improvement of asymmetrical characteristics in submicron CMOS devices

AbstractIn the substrate current characteristics and the drain current characteristics in a submicron nMOSFET with an LDD structure, the problem of asymmetry caused by ion implantation occurs if the measurement is done with the source and drain interchanged. It is found also that significant asymmetry appears in the subthreshold current characteristics (threshold voltage) in a submicron pMOSFET with EPS (efficient punchthrough stops). By introducing the four‐step implantation method as a technique to form LDD and EPS regions, an attempt was made to improve asymmetry. By this method, symmetric electrical characteristics are obtained without changing the conventional process and without reducing the throughput. Further, the unbalance of the threshold voltages between the pair transistors was measured because they have the greatest effect on the sensitivity of the sense amplifier important in the VLSIDRAM. It was found that the four‐step implantation method is extremely effective for suppressing the asymmetry without changing the circuit design.

A new isolation method with boron-implanted sidewalls for controlling narrow-width effect

A new isolation method for high packing density MOS devices has been developed. In this method the LOCOS technique is applied to wide isolation regions and the buried-oxide technique is applied to isolation regions less than 2 µm wide. No additional masks are needed in order to form SiO 2 film in the wide field regions because the photoresist is thicker near steps and inside the narrow trenches. For reducing the hump that appears in subthreshold current characteristics of n-channel MOSFET's, Using buried-oxide isolation, tilt-angle implantation to each of the four sidewalls is performed as a channel stop. The Sidewall channel stop can also control the narrow-channel effect.

Analysis of an anomalous subthreshold current in a fully recessed oxide MOSFET using a three-dimensional device simulator

This paper describes a three-dimensional device simulator, TOPMOST, and its use in the analysis of the anomalous subthreshold current "hump" in a fully recessed oxide MOS structure. TOPMOST solves Poisson's and current continuity equations using the finite-difference method and the box-integration technique, which has been extended to suit an arbitrary three-dimensional structure. The device simulator can be optionally coupled with a two-dimensional process simulator for investigating the influence of process conditions on device performances. Using TOPMOST, the subthreshold current characteristics of a fully recessed oxide structure are examined. The mechanism underlying the hump is clarified, and the dependence on structure parameters, such as channel width, gate oxide thickness, and gate extension, are studied. It is shown that there is a worst case where the current hump becomes most conspicuous. It is also shown that the hump can be suppressed by a side-wall implantation.

Analysis of an Anomalous Subthreshold Current in a Fully Recessed Oxide MOSFET Using a Three-Dimensional Device Simulator

This paper describes a three-dimensional device simulator, TOPMOST, and its use in the analysis of the anomalous subthreshold current "hump" in a fully recessed oxide MOS structure. TOPMOST solves Poisson's and current continuity equations using the finite-difference method and the box-integration technique, which has been extended to suit an arbitrary three-dimensional stucture. The device simulator can be optionally coupled with a two-dimensional process simulator for investigating the influence of process conditions on device performances. Using TOPMOST, the subthreshold current characteristics of a fully recessed oxide structure are examined. The mechanism underlying the hump is clarified, and the dependence on structure parameters, such as channel width, gate oxide thickness, and gate extension, are studied. It is shown that there is a worst case where the current hump becomes most conspicuous. It is also shown that the hump can be suppressed by a side-wall implantation.

Subthreshold design considerations for insulated gate field-effect transistors

A knowledge of subthreshold behavior in an insulated gate field-effect transistor is important for circuits with low leakage specifications. This paper discusses the effect of drain voltage on the subthreshold region as the channel length becomes shorter, the effect of substrate bias on both the shift in and the slope of the subthreshold curves, and the effect of temperature on the subthreshold current characteristics. It is shown that all these effects can be incorporated into a simple one-dimensional model.