Subthreshold CMOS Voltage Reference Research Articles

A 1 V supply 10.3 ppm/°C 59 nW subthreshold CMOS voltage reference

—A low temperature coefficient (TC), low power subthreshold CMOS voltage reference (CVR) over a wide temperature range is presented in this paper. The proposed circuit employs the voltage difference between the two inputs of the operational amplifier as the proportional to absolute temperature (PTAT) voltage and the complementary to absolute temperature (CTAT) voltage, which is obtained by the ΔVGS of different-threshold transistors biased in the subthreshold region. The proposed CVR was designed in the 0.18-μm CMOS process with a total area of 0.0049 mm2. It achieves an average temperature coefficient (TC) of 10.3 ppm/°C over a temperature range of −40 °C–120 °C, with a TC of 4.9 ppm/°C at the TT corner. The measured power supply rejection ratio (PSRR) is −65 dB at 10 Hz and −30 dB at 1 MHz, while the power consumption is 59 nW at a supply voltage of 1 V. The average line sensitivity (LS) is 0.16 %/V, and the LS is 0.09 %/V at the TT corner.

A 8.83 ppm/°C temperature coefficient, 75 dB PSRR subthreshold CMOS voltage reference with piecewise curvature compensation

A subthreshold CMOS voltage reference (CVR) with low temperature coefficient (TC) over a wide temperature range and low power is proposed in this paper. The proposed CVR utilizes the ΔVGS of different-threshold and same-threshold nMOS pairs to generate complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages, respectively. To compensate for the low-temperature and high-temperature segments of the temperature characteristic curve, the nonlinear compensation currents generated by the exponential-like relationship between the drain current and the gate-source voltage of two MOSFETs work in the subthreshold region is used. Based on a 0.18-μm CMOS process, post-layout simulation results show that the proposed CVR achieves an average output voltage of 263 mV. The power supply ripple rejection (PSRR) is −75 dB at 10 Hz and the line sensitivity (LS) is 0.0069 %/V when the supply voltage varies from 0.8 V to 2.5 V. The average TC is 8.83 ppm/°C for a wide temperature range of −40 °C–120 °C, and the minimum TC is only 3.65 ppm/°C.

A 1.65‐nW 11.14‐ppm/°C self‐biased subthreshold CMOS voltage reference with temperature compensation circuit

SummaryThis paper presents a subthreshold CMOS voltage reference (VR) that utilizes self‐biased circuits. This voltage reference includes temperature compensation circuits to expand its operating temperature range and reduce its temperature coefficient. The proposed CMOS voltage reference is designed using a standard 0.18‐μm CMOS process and has a small area of only 0.005 mm2. Post‐layout simulation results demonstrate that the power consumption of the circuit at room temperature (25°C) is only 1.65 nW at a power supply voltage of 1 V. In this case, the voltage reference output is 316.56 mV, with an average temperature coefficient (TC) of 11.14 ppm/°C in a wide temperature range from −40°C to 140°C. Furthermore, the line sensitivity (LS) of the circuit is 0.024%/V, and the power supply rejection ratio (PSRR) of the circuit is −86.5 dB at 10 Hz. In summary, the subthreshold CMOS voltage reference structure proposed in this paper demonstrates excellent performance characteristics, such as low power consumption, a small area, and high‐temperature stability. These features make it a promising candidate for voltage reference for low‐power applications with significant changes in environmental temperature.

A picowatt, 3.88 ppm/°C, 0.011%/V subthreshold CMOS voltage reference biased by GSCC current source

A picowatt, 3.88 ppm/°C, 0.011%/V subthreshold CMOS voltage reference biased by GSCC current source

3.48-nW 58.4ppm/°C Sub-threshold CMOS Voltage Reference with Four Transistors and Two Resistors

In this paper, an ultra-low power CMOS voltage reference capable of operating at sub-1[Formula: see text]V input supply is proposed. Four transistors biased in weak inversion are used to generate the required complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages of the proposed circuit. Self-biasing of nature of the proposed configuration in the form of operational amplifier (opamp)-free ensure nano-power operation and eliminate the need for lateral bipolar junction transistors (BJTs) and offset cancelation techniques. A prototype of the circuit is designed and simulated in a standard 0.18-[Formula: see text]m CMOS process. Post-layout simulation results show that the circuit generates a reference voltage of 494[Formula: see text]mV with temperature coefficient (TC) of 58.4[Formula: see text]ppm/∘C across [Formula: see text]C to 85∘C; while the consuming power is lowered to 3.48[Formula: see text]nW at the minimum supply of 0.8[Formula: see text]V. The line sensitivity is 0.7%/V for the supply voltages from 0.8[Formula: see text]V to 1.8[Formula: see text]V, whereas the power supply ripple rejection (PSRR) is [Formula: see text]49.06[Formula: see text]dB at 1[Formula: see text]Hz. Monte Carlo simulation results of the voltage reference show a mean value of 497.2[Formula: see text]mV with [Formula: see text]/[Formula: see text] of 1.7%, demonstrating the robustness of the generated reference voltage against the process variations and mismatch.

A Low Supply Voltage, Low Line Sensitivity and High PSRR Subthreshold CMOS Voltage Reference

The paper presents a low supply voltage CMOS voltage reference with low line sensitivity and high PSRR. Generally, the reference voltage is obtained using both complementary-to-absolute-temperature (CTAT) current and proportional-to-absolute-temperature (PTAT) current. This technique increases the complexity and area of the reference circuit. To overcome these drawbacks, the temperature compensated reference voltage has been proposed using only CTAT currents. Mostly, the CTAT current generators are simple, power-efficient, and area-efficient as compared to the PTAT current generators. The negative feedback loop has been formed in the proposed design to obtain a supply independent CTAT current and to avoid the use of startup drivers. The proposed circuit has been designed using Cadence virtuoso analog design environment in BSIM3V3 180[Formula: see text]nm CMOS technology. The simulation results of the proposed circuit show a reference voltage of 312[Formula: see text]mV with a temperature coefficient (TC) of 38.85[Formula: see text]ppm/∘C over a wide temperature range of [Formula: see text]C to 125∘C with a supply voltage of 0.8[Formula: see text]V. The line sensitivity is 0.027% [Formula: see text] with a supply voltage ranging from 0.8[Formula: see text]V to 3[Formula: see text]V. The power supply rejection ratio (PSRR) without using any capacitive filter is observed as [Formula: see text] and [Formula: see text][Formula: see text]dB at 100[Formula: see text]Hz and 100[Formula: see text]kHz frequency, respectively. The circuit is simple and occupies a chip area of 0.0027[Formula: see text]mm2.

A 0.6V 44.6 ppm/ºC subthreshold CMOS voltage reference with wide temperature range and inherent leakage compensation

In this paper, a 0.6 V subthsheshold CMOS voltage reference (CVR) achieving wide temperature range and high power supply ripple rejection (PSRR) is presented. The proposed CVR structure can compensate the high temperature leakage and current mirror induced mismatches so as to increase the operating temperature range. The generated reference voltage of the proposed CVR circuit is the threshold voltage difference of two NMOS transistors, leading to relatively small variations. Moreover, the enhanced current source helps achieve high PSRR. The proposed CVR circuit is implemented in a standard 0.18-μm CMOS technology. Measurement results show that, with one single trimming, a mean output of 344 mV with standard deviation of only 2.89 mV and average TC of 44.6 ppm/°C over a wide temperature range from −40 °C to 125 °C is achieved. The measured PSRR is −68 dB, −52 dB and −52 dB at 10 Hz, 100 kHz and 10 MHz, respectively. The measured line sensitivity (LS) is 0.06%/V with a power supply from 0.6 V to 2 V while consuming 19.8 nW at 0.6 V supply. The active area is 0.019 mm2.

A 48 pW, 0.34 V, 0.019%/V Line Sensitivity Self-Biased Subthreshold Voltage Reference With DIBL Effect Compensation

This paper presents a self-biased subthreshold CMOS voltage reference for low-power and low-voltage applications. To achieve near-zero line sensitivity and high PSRR, a compensation structure utilizing the drain-induced-barrier-lowering (DIBL) effect is proposed to sink a supply dependent current from the output branch of a self-biased CMOS reference, which cancels the bias current’s dependence on the supply voltage due to the DIBL effect. Fabricated in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology, the measurement results demonstrate that the proposed circuit could operate under a minimum supply voltage of 0.34 V and generate a reference voltage of 147 mV, while consuming only 48 pW power. The PSRRs measured at 1 Hz and 10 kHz are −70.6 dB and −50.2 dB, respectively. For 39 measured samples, the mean line sensitivity is 0.019%/V in a supply voltage range from 0.34 to 1.8 V, and the average temperature coefficients before and after trimming are 64.81 and 10.06 ppm/°C in 0 ~ 100 °C temperature range, respectively. The total area of the voltage reference circuit is 0.0332mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 0.6-V Minimum-Supply, 23.5 ppm/°C Subthreshold CMOS Voltage Reference With 0.45% Variation Coefficient

In this brief, a low-voltage low-temperature- coefficient (TC) subthreshold CMOS voltage reference (CVR) is presented. The proposed CVR employs the ${\Delta }\text{V}_{\mathbf{GS}}$ of different-threshold and same-threshold nMOS transistor pairs to generate the complementary-to-absolute-temperature and proportional-to-absolute-temperature voltages, respectively. Low TC with small variations and high power supply ripple rejection (PSRR) are achieved. The proposed design is fabricated in a standard 0.18- $ {\mu }\text{m}$ CMOS process. It measures an average reference voltage of 218.3 mV with a deviation of 0.97 mV and variation coefficient of 0.45%. It achieves an average TC of 23.5 ppm/°C for a temperature range of −40 °C to 125 °C. The measured PSRR is −66.4 dB, −42.4 dB and −42.3 dB at 10 Hz, 1 kHz and 10 MHz, respectively. The measured line sensitivity is 0.40%/V for 0.6 V to 2.0 V supply. The consumed power is 30.5 nW at 0.6-V supply.

Picowatt, 0.45–0.6 V Self-Biased Subthreshold CMOS Voltage Reference

In this paper, a self-biased temperature-compensated CMOS voltage reference operating at picowatt-level power consumption is presented. The core of the proposed circuit is the self-cascode MOSFET (SCM) and two variants are explored: a self-biased SCM (SBSCM) and a self-biased NMOS (SBNMOS) voltage reference. Power consumption and silicon area are remarkably reduced by combining subthreshold operation with a self-biased scheme. Trimming techniques for both circuits are discussed aiming at the reduction of the process variations impact. The proposed circuits were fabricated in a standard 0.18- $\mu \text{m}$ CMOS process. Measurement results from 24 samples of the same batch show that both circuits herein proposed can operate at 0.45/0.6 V minimum supply voltage, consuming merely 55/184 pW at room temperature. Temperature coefficient (TC) around 104/495 ppm/°C across a temperature range from 0 to 120 °C was measured. Employment of a trimming scheme allows a reduction of the average TC to 72.4/11.6 ppm/°C for the same temperature range. Both variants of the proposed circuit achieve a line sensitivity of 0.15/0.11 %/V and a power supply rejection better than −44/−45 dB from 10 to 10 kHz. In addition, SBSCM and SBNMOS prototypes occupy a silicon area of 0.002 and 0.0017 mm2, respectively.

Sub-1 V, pico-watt subthreshold CMOS voltage reference circuit with dual temperature compensation

A pico-watt CMOS voltage reference is developed using an SK Hynix 0.18µm CMOS process. The proposed architecture is resistorless and consists of MOSFET circuits operated in the subthreshold region. A dual temperature compensation technique is utilized to produce a near-zero temperature coefficient reference output voltage. Experimental results demonstrate an average reference voltage of 250.7mV, with a temperature coefficient as low as 3.2ppm/°C for 0 to 125°C range, while the power consumption is 545pW under a 420mV power supply at 27°C. The power supply rejection ratio and output noise without any filtering capacitor at 100Hz are −54.5dB and 2.88µV/Hz1/2, respectively. The active area of the fabricated chip is 0.00332mm2.

A Sub-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;${\boldsymbol kT}/\boldsymbol q$ &lt;/tex-math&gt;&lt;/inline-formula&gt; Voltage Reference Operating at 150 mV

We propose a subthreshold CMOS voltage reference operating with a minimum supply voltage of only 150 mV, which is three times lower than the minimum value presently reported in the literature. The generated reference voltage is only 17.69 mV. This result has been achieved by introducing a temperature compensation technique that does not require the drain–source voltage of each MOSFET to be larger than $4 kT/q$ . The implemented solution consists in two transistors voltage reference with two MOSFETs of the same threshold-type and exploits the dependence of the threshold voltage on transistor size. Measurements performed over a large sample population of 60 chips from two separate batches show a standard deviation of only 0.29 mV. The mean variation of the reference voltage for $V_{\rm DD}$ ranging from 0.15 to 1.8 V is 359.5 $\mu $ V/V, whereas the mean variation of V $_{\rm {REF}}$ in the temperature range from 0 °C to 120 °C is 26.74 $\mu $ V/°C. The mean power consumption at 25 °C for $V_{\rm DD}= 0.15$ V is 26.1 pW. The occupied area is $1200~\mu $ m $^{2}$ .

250-mV Supply Subthreshold CMOS Voltage Reference Using a Low-Voltage Comparator and a Charge-Pump Circuit

This brief proposes a subthreshold CMOS voltage reference circuit, which reduces the minimum supply voltage by replacing the analog amplifier in the conventional CMOS voltage reference circuit with a low-voltage comparator, a charge-pump circuit, and a digital control circuit. The subthreshold CMOS voltage reference circuit was fabricated using a 0.11-μm CMOS process. Its core area was 0.013 mm 2 and it consumed 5.35 μW at V DD = 250 mV and f CLK = 1 MHz. Its minimum supply voltage was 242 mV. Ten sample chips generated 193-207-mV reference voltage with 0.4-3.2-mV/100-mV line sensitivity at V DD = 250-400 mV and 58-186 ppm/°C temperature coefficient at 10 °C-90 °C.