Substrate Stack Research Articles

Highly reproducible and CMOS-compatible VO2-based oscillators for brain-inspired computing.

With remarkable electrical and optical switching properties induced at low power and near room temperature (68°C), vanadium dioxide (VO2) has sparked rising interest in unconventional computing among the phase-change materials research community. The scalability and the potential to compute beyond the von Neumann model make VO2 especially appealing for implementation in oscillating neural networks for artificial intelligence applications, to solve constraint satisfaction problems, and for pattern recognition. Its integration into large networks of oscillators on a Silicon platform still poses challenges associated with the stabilization in the correct oxidation state and the ability to fabricate a structure with predictable electrical behavior showing very low variability. In this work, the role played by the different annealing parameters applied by three methods (slow thermal annealing, flash annealing, and rapid thermal annealing), following the vanadium oxide atomic layer deposition, on the formation of VO2 grains is studied and an optimal substrate stack configuration that minimizes variability between devices is proposed. Material and electrical characterizations are performed on the different films and a step-by-step recipe to build reproducible VO2-based oscillators is presented, which is argued to be made possible thanks to the introduction of a hafnium oxide (HfO2) layer between the silicon substrate and the vanadium oxide layer. Up to seven nearly identical VO2-based devices are contacted simultaneously to create a network of oscillators, paving the way for large-scale implementation of VO2 oscillating neural networks.

Solid and Liquid State Dewetting of Thin Silicon Films Sandwiched between Two Silicon Carbide Substrates

Silicon carbide (SiC) is a very promising material for power electronics thanks to its wide band gap and high thermal conductivity. Stacking of SiC substrates of different crystalline quality and/or doping levels through wafer bonding is of particular interest for applications. Although a direct SiC/SiC bonding may result in an unstable interface, a layer of intermediate material playing a role of a “glue” can be sandwiched between the SiC substrates to ensure their good attachment. However, the processing of the power electronics devices at a high temperature may degrade the properties of this material which evolution under high temperature annealing must be studied in advance.In this work, we exploited the possibility to use silicon (Si) as a bonding material. We studied the structure evolution of a nanometer-thick polycrystalline Si layer sandwiched between two monocrystalline SiC substrates with a high temperature annealing. We focused our attention on understanding the impact of as-bonded Si layer thickness and the temperature of annealing on the eventual Si layer morphology. Tests were conducted for Si films of as-bonded thickness of 8 nm, 20 nm and 40 nm at temperatures ranging from 950°C to 1400°C, i.e. below Si melting temperature of 1414°C, and above it up to 1700°C. The experiments were realized using transmission electron microscopy (TEM), scanning electron microscopy (SEM) and high-resolution X-ray diffraction techniques. Cross-sectional TEM images were used to describe the structure and morphology of the interface. SEM was used to observe the inner surface of one of the SiC substrates once the other was removed by a cleavage. X-ray measurements were carried out to determine Si film thickness and texture as well as the strain in Si and SiC.We show that annealing at temperatures ranging from 950°C to 1400°C results in pitting, i.e. creation of voids, at the Si/SiC interfaces which are observed for any studied as-bonded thickness of a Si layer. We attribute this effect to a solid state dewetting of Si from SiC. This dewetting effect evolves into complete piercing of the silicon film and formation of cylindrical voids within the Si layer which grow in diameter with annealing temperature. We also observe a thickening of the silicon layer. The driving force for a solid state dewetting will be discussed in terms of SiC/Si interface energy, vacancies precipitation and Si atoms diffusion.When annealed to relatively higher temperatures allowing for Si melting followed by its solidification, we put into evidence the formation of step bunching on the internal surfaces of both SiC substrates. Regarding Si, it is concentrated along the SiC steps. The mechanism of the reconstruction of SiC internal surfaces resulting in the creation of step bunching will be discussed in relation to Si liquid state dewetting, carbon atoms dissolution, recondensation and migration within liquid Si.The effect of as-bonded silicon film thickness on the Si dewetting process is not pronounced after annealing at 950°C: all samples contain pits of a similar size and density. When the annealing temperature is slightly increased above 1000°C, the pits in the Si films of a lower initial thickness transform into cylindrical voids piercing the layers. The thicker layers contain both pits and cylindrical voids. At a high enough temperature of 1400°C only cylindrical voids were observed in all samples. The thicker layers present the lowest densities of voids.For the annealing at temperatures higher than 1400°C, the as-bonded thickness of a Si layer had a direct impact on the height of the steps formed on the internal surfaces of the SiC substrates. The eventual steps were higher the thicker the Si layer was used for bonding.The role of the diffusion and interaction of Si and C atoms and vacancies during annealing will be discussed in relation to the dynamics of solid and liquid state Si dewetting, size and density of pits and cylindrical voids and eventual Si layer morphology.Figure 1, on the left, SEM images showing the evolution of Si solid state dewetting with annealing temperature, from pitting to the formation of cylindrical voids. On the right, SEM and cross-sectional TEM images showing the step bunching on the SiC internal surfaces and the Si accumulation at the steps obtained after Si liquid state dewetting. Figure 1

Methodology to Characterize Thermal Properties of Thin Film Superconductors Using a DynaCool Physical Property Measurement System

We describe a methodology to characterize heat capacity <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C<inline-formula><tex-math notation="LaTeX">$_{p}$</tex-math></inline-formula></b> of 1 μm thick Nb thin films at a temperature range of 60 K to 1.8 K. We used a commercially available relaxation calorimeter device by Quantum Design DynaCool Physical Property Measurement System (PPMS). The mass of thin films is negligible compared to the minimum coarse estimate required by the heat capacity module of the PPMS. To overcome this limitation, a vertical stack of multiple diced substrates of the same material with uniform dimensions of 2.5 mm x 2.5 mm was joined by cryogenically compatible grease to form a stack resulting in a larger effective mass of the target film. The critical behavior of heat capacity in the region of the transition temperature is demonstrated. The heat capacity of Nb thin films was measured by subtracting the total heat capacity of the joining grease and stack of substrate used as addenda. Results in this work prove that a vertical stacking approach is viable for measuring the behavior of deposited thin films.

Simulation study on physical parameters ruling unipolar resistance switching of sputter-deposited silicon oxide film on Si substrate

This paper performs Monte Carlo simulations to elucidate the physical parameters that rule the unipolar switching process in sputter-deposited Si oxide films, where the metal/sputter-deposited Si oxide film/Si substrate stack structure is assumed. Simulation parameters are based on the results of experiments performed in parallel. Generations of simple bond breaking, oxygen vacancies, metallic Si sites, and E″ centers are implemented in the simulation algorithm, where various chemical parameters are used to control bonding conditions. In this study, the impact of hole injection from the Si substrate on the switching operation is also discussed. All-positive voltage stress mode for both the electroforming process (or set process) and the reset process and all-negative voltage stress mode for both the electroforming process (or set process) and the reset process are compared in detail as to their effect on the film’s degradation process.The comparison of the two different stress modes reveals that the positive stress mode does not yield devices with stable, repeatable switching. On the other hand, the negative stress mode results in stable, repeatable switching. It is strongly suggested that the difference stems from the physical asymmetry of the electrode materials; that is, the energy spectra of electrons injected from the Si substrate has a wide range in the all-positive stress mode and the energy transfer efficiency from electrons injected from Si substrate to the atomic bonding sites is small due to the large tunnel probability, which does not result in the successful switching of the Si oxide film. The role of hole injection from the n-Si substrate on the negative-stress-mode switching process is also discussed. These new findings should contribute to the design methodology of such resistance switching devices.

Broadband dual‐podal multilayer Vivaldi antenna array for remote sensing applications

AbstractA novel wideband multilayer dual‐podal Vivaldi antenna with broadband characteristics from 5.5 to 20.82 GHz, is presented. Contrary to traditional Vivaldi antennas that are antipodal‐based, this design is realised by placing a pair of podal Vivaldi antennas with corrugated slots on the top and bottom of a substrate stack (consisting of two dielectric layers) using a Bondply. The pair is fed in‐phase with the help of a Strip‐Line (SL) transmission section that is terminated on a radial stub to couple capacitively to the antenna elements. With this technique of electrically coupling a podal Vivaldi pair, improved performance parameters are achieved, specifically: a measured maximum gain of 9.33 dBi, Half Power Beam Width of 126.5° in the H‐plane, and a maximum Front‐to‐Back (F/B) ratio of 14.36 dB with an overall antenna size of 29 × 21 × 1.63 mm. The in‐depth understanding of the working mechanism is supported by a detailed parametric analysis, current distribution, and a clear physical insight into the operating principles. Moreover, a 1 × 4 Vivaldi antenna array is also designed and analysed. A measured maximum gain of the 13 dBi at 15 GHz in the array is achieved along with the wide bandwidth of 6.3 GHz from 10.78 to 17.07 GHz. The array is fed through an SL corporate feed network that ensures in‐phase excitation of all four Vivaldi pairs. A Grounded Co‐planar Waveguide to SL transition is adopted for connecting the 2.92 mm Radio Frequency launcher on the top layer. The very compact geometry of the proposed structure enables its integration into the systems for remote sensing applications.

A Transient Resistance/Capacitance Network-Based Model for Heat Spreading in Substrate Stacks Having Multiple Anisotropic Layers

Abstract Heat spreading from local, time-dependent heat sources in electronic packages results in the propagation of temperature nonuniformities through the stack of material layers attached to the chip. Available models either predict the chip temperatures only in the steady-state or a single substrate for transient analysis, without the ability to predict the transient response in compound substrates having multiple anisotropic layers. We develop a transient resistance/capacitance network-based modeling approach capable of predicting the spatiotemporal temperature fields for this chip-on-stack geometry, accounting for in-plane heat spreading, through-plane heat conduction, and the effective convection resistance boundary conditions. The transient heat spreading resistance for an anisotropic substrate has been formulated by converting it to an effective isotropic substrate for which there is an available half-space solution. The transient heat spreading model for a step heat input to a single substrate is subsequently extended to any arbitrary transient heat input using a Fourier series and extending the half-space formulation from a step heat input to sinusoidal heat input. For obtaining the transient spreading resistance for heat inputs into multiple stacked substrates, a method has been outlined to convert the multisubstrate stack to a single substrate with effective isotropic properties by properly accounting for the in-plane and through-plane thermal conductivities, and the heat capacity. The estimates from the present model are validated with direct comparison to a finite volume numerical model for three-dimensional heat conduction. Case studies are presented to demonstrate the capabilities of the proposed network-based model and compare its estimates with the numerical conduction solution. In the presence of a step heat input, the results demonstrate that the model accurately captures the transient temperature rise across the multisubstrate stack comprising layers with different anisotropic properties. For a case where the rectangular stack is exposed to a sinusoidally varying heat input, the model is able to capture the general trends in the transient temperature fields in the plane where the heat source is applied to the multisubstrate stack. In summary, the developed resistance/capacitance network-based transient model offers a low-computational-cost method to predict the spatiotemporal temperature distribution over an arbitrary transient heat source interfacing with a multilayer stack of substrates.

Reliability Analysis of Large-Area, Low-Pressure-Assisted Silver Sintering for Medium-Voltage Power Modules

Multi-layer insulating ceramic substrates can enable medium-voltage (MV) power modules with reduced peak electric field. This benefit is particularly important for MV silicon carbide (SiC) MOSFETs due to their higher operating voltages. Large-area, low-pressure-assisted silver sintering is a potential solution for bonding substrates to create a multi-layer structure. The voiding content and defect density of the bond used to create the multi-layer substrate stack-up are critical to the reliability of the power module and thermal performance, as this bond is in the primary path for heat dissipation in the power module structure. Samples of two-layer direct bonded aluminum (DBA) stacks have been fabricated and subjected to thermal cycling to analyze their reliability. Passive thermal cycling from −40 °C to 200 °C was performed. Cross sections were cut at pre-determined intervals and imaged with scanning electron microscopy (SEM). After 1000 thermal cycles, adhesive failures are observed between the sintered silver and DBA surface. Cross sections were cut and imaged via optical microscope and SEM. Thermal analyzer measurements are recorded on a 10-kV SiC power module using the sintered DBA substrate stacks.

Using electron channeling contrast imaging to inform and improve the growth of high-efficiency GaAs solar cells on nanopatterned GaAs substrates

Patterned substrates provide opportunities for reducing the cost of high-efficiency III-V devices by incorporating mechanically weak layers beneficial for substrate reuse (e.g. by spalling). In this work, the functionality of electron channeling contrast imaging (ECCI) as a tool to efficiently understand and mitigate defect formation is exemplified by developing a process in which high-quality III-V material can be grown on nanopatterned GaAs substrates. Reactive ion etching used in the patterning process was found to damage the GaAs substrate surface, leading to the formation of stacking faults in the epitaxial material as observed by ECCI. Etching the patterned substrates in a 1 NH4OH: 1 H2O2: 50 DI H2O solution for 10 s prior to growth removed the substrate surface damage and stacking faults were no longer present. Growth of solar cell device structures initially produced samples with many macroscale flaws creating shunts in the devices, which complicated the assessment of material quality by device measurements. However, ECCI revealed that the epitaxial material surrounding macroscale flaws was free from any crystallographic defects such as stacking faults and threading dislocations. With this knowledge, we focused on refining the patterning process to eliminate the macroscale flaws. Solar cells were then grown on the improved nanopatterned substrates and exhibited device structures with defect densities less than 5 × 105 cm−2 and average conversion efficiency of 24.8%, nearly identical to devices grown on unpatterned epi-ready substrates (25.0%).

Laminated Glass-Based, Compact Inline Stepped-Impedance Resonator Bandpass Filters for 5G New Radio Modules

Miniaturization of millimeter-wave (mm-wave) filters relies on innovative designs that require fine lines and spacings. These designs drive the need for precision fabrication that cannot be achieved with traditional laminates or cofired ceramics. This gives unique performance justification to glass substrate technologies for future integrated mm-wave components because of both superior performance and 3– $5\times $ reduction in volume. In this letter, laminated glass-based compact inline stepped-impedance resonator (SIR) filters are presented for 5G new radio (NR) modules. The frequency bands of interest are 5G NR bands: n257 and n260. The filters are designed using microstrip transmission lines with the fourth-order quasi-elliptic response with skew-symmetric feed. The enhanced transition responses of these filters provide transmission zeros (TZs) on either side of the passband. When these filters are designed for mm-wave applications, their dependence on the accuracy of metal patterns increases significantly due to narrow linewidth and spacing requirements to realize moderate fractional bandwidths. Two inline SIR filters are fabricated using a large-area, panel-compatible semiadditive patterning (SAP) process on precision redistribution layers (RDLs) of a laminated glass substrate stack up. The sensitivity of these filters to the dimensional variations of patterned copper is analyzed, and the discrepancy between simulated and measured response of the filters is studied by performing postfabrication simulations.

Excitation Light Energy Dependence of Silver Photodiffusion into Amorphous Germanium Sulfide: Neutron and X‐Ray Reflectivity and X‐Ray Diffraction

Silver photodiffusion into amorphous chalcogenides is the photoinduced phenomenon, in which mobile Ag ions are injected into semiconductor films, and is applicable to nonvolatile memory devices. To understand the role of light illumination in the silver diffusion into a chalcogenide layer, the excitation light energy dependence of silver photodiffusion in Ag/a‐Ge20S80/Si substrate stacks is investigated by neutron reflectivity, X‐ray reflectivity, and X‐ray diffraction. The measurements reveal that there is an energy threshold to induce silver photodiffusion, which corresponds to the optical gap of amorphous Ge20S80. The excitation of the lone‐pair electrons to the antibonding states by the light illumination with greater energy than the optical gap leads to the bond breaking, and the Ge–S network structure is reorganized involving Ag ions.

Silver photodiffusion into amorphous Ge chalcogenides

Silver photodiffusion into amorphous chalcogenides involves the movement of ions controlled by a UV-visible light illumination, and has potential application to memory devices. Understanding the kinetics of this phenomenon will expand the range of possible applications. Herein, we report the excitation photon energy dependence of the silver photodiffusion kinetics in Ag/amorphous Ge20S80/Si substrate stacks, probed by neutron reflectivity using four light-emitting diodes with different peak wavelengths. Time-dependent changes were clearly observed in all three of the Ag/Ag-doped reaction/chalcogenide host layers, in terms of layer thickness, scattering length density, and roughness. Silver photodiffusion effectively occurred when the excitation photon energy was greater than the optical gap of the chalcogenide host material. Excitation of lone-pair electrons to anti-bonding states at the chalcogenide layer therefore appears to play a crucial role in triggering silver photodiffusion.

Porous Silica Nanotube Thin Films as Thermally Insulating Barrier Coatings

The fabrication and examination of a porous silica thin film, potentially for use as an insulating thin film, were investigated. A vertically aligned carbon nanotube (CNT) forest, created by chemical vapor deposition (CVD), was used as scaffolding to construct the porous film. Silicon was deposited on the CNT forest using low-pressure CVD (LPCVD) and then oxidized to remove the CNTs and convert the silicon to silica for electrical or thermal passivation (e.g., thermal barrier). Thermal conductivity was determined using a 1D heat-transfer analysis that equated radiative heat loss in a vacuum with conduction through the substrate and thin film stack. A comparison of the surface temperature differences between a sample film and a reference of comparable thermal resistance enabled determination of the increase in the thermal resistance and of the thermal conductivity of the films. For film thicknesses of approximately 55 μm, the cross-plane thermal conductivity was found to be 0.054–0.071 W m–1 K–1 over 378–422 K. This thermal conductivity value is in the range of other silica aerogels and consistent with the low gravimetric density of 0.15 g cm–3 for the samples. The film is also relatively smooth and flat, with an average arithmetic mean roughness of 1.04 μm.

Graphene‐Based Carbocatalysts for Thermoset Polymers and for Diastereoselective and Enantioselective Organic Synthesis

AbstractThis review reports on the catalytic activity of graphene oxide (GO) and high‐surface‐area graphite (HSAG) for some relevant organic reactions. It is shown that the main drawbacks of graphite‐based catalysts, that is, high catalyst loading and generally poor selectivity, can often be removed by operating under solvent‐free conditions. Moreover, some reactions that are catalyzed by GO as well as HSAG are presented. For these reactions, π stacking of the aromatic substrates with the graphitic planes plays a predominant role in the catalytic activity and the unexpected diastereoselective and enantioselective behaviors.

Effect of Y and Mn doping into rutile type TiO2/Ge stack structure by combinatorial synthesis

The effects of Y and Mn doping into the rutile TiO2 films on a (100) Ge substrate stack structure were investigated by combinatorial synthesis. Composition spread films were fabricated by combinatorial pulsed laser deposition. Regardless of the dopant concentration, the Mn-doped TiO2 film indicated an amorphous structure. In contrast, the Y-doped TiO2 film had a rutile-type crystal structure below an Y concentration of 11.0 at. %. The high Y concentration enhanced the amorphous structure and Ge diffusion into the TiO2 layer. Although both dopants reduced leakage currents, the effect of Y was greater than that of Mn. The post-deposition annealed Y-doped TiO2 indicated an improvement in the leakage current by three orders of magnitude and electron accumulation at a capacitor structure. The Y doping into TiO2 may provide beneficial effects of good interface control and effective dielectric material for Ge-based capacitors.

Negative-tone Photodefinable Underfill Having High Resolution and Appropriate Thermal Fluidity

Photodefinable wafer level underfill (PWLUF) has been evaluated for chip to substrate stacking. The good fluidity of PWLUF after patterning is required for chip and substrate stacking. PWLUF was designed using polyimide, acrylates, epoxides and some additives. It was difficult to improve the fluidity of patterned PWLUF keeping resolution by changing the composition ratio of acrylates and epoxides. On the other hand, PWLUF using the polyimide oligomer obtained by increasing end capping agent ratio improved the fluidity as well as the resolution. The chip to substrate stacks afford void-free bump soldering without underfill entrapment. We also successfully demonstrated the reflow soldering process using PWLUF.

Ultra-Thin Rechargeable Lithium Ion Batteries on Flexible Polymer: Design, Low Temperature Fabrication and Characterization

In this work we developed flexible rechargeable thin film lithium ion batteries based on all-solid-state materials. The flexible batteries were fabricated using low temperature sequential physical vapor deposition techniques. A thin film battery (TFB) architecture consisting of Ti/V2O5/LiPON/Li/encapsulation multilayer was deposited on flexible polyimide substrate. To the best of our knowledge, the obtained TFBs are among the thinnest reported with an overall thickness of 50 μm including substrate, active layers and encapsulation stack. The fabricated TFBs delivered discharge capacity as high as 0.15 mAh (1.5 cm² of cathode area) upon galvanostatic cycling at 30 μA.cm−2 within 3.8–1.5 V voltage range. The capacity decreased during cycling with an average fading rate of 0.25% over 100 cycles. Electrochemical impedance spectroscopy (PEIS) measurements and modeling analysis revealed an increase of the internal resistance during cycling. Furthermore, it was shown that the internal resistance increase was induced by a progressive decrease of the electrolyte/electrodes contact area. TFBs having the same architecture and cell design were fabricated on two substrates: a flexible polyimide foil and a rigid silicon wafer. Electrochemical characterization showed a clear influence of substrate type on TFBs discharge capacity and internal resistance variations during cycling, the results are discussed within this paper

Silver photo-diffusion and photo-induced macroscopic surface deformation of Ge33S67/Ag/Si substrate

Ge-chalcogenide films show various photo-induced changes, and silver photo-diffusion is one of them which attracts lots of interest. In this paper, we report how silver and Ge-chalcogenide layers in Ge33S67/Ag/Si substrate stacks change under light exposure in the depth by measuring time-resolved neutron reflectivity. It was found from the measurement that Ag ions diffuse all over the matrix Ge33S67 layer once Ag dissolves into the layer. We also found that the surface was macroscopically deformed by the extended light exposure. Its structural origin was investigated by a scanning electron microscopy.

A Novel Bonding Approach and Its Electrical Performance for Flexible Substrate Integration

A novel bonding approach for flexible substrate vertical stacking is proposed in this paper. Unlike the traditional anisotropic conductive/non-conductive paste/film used in flexible substrate bonding, the metal thin film is adopted as bonding material in this approach. Experiment results show that the novel bonding approach has good electrical properties and reliability performances. The innovative bonding approach is considered a breakthrough of the traditional restrictions in flexible substrates, including I/O pitch, electrical reliability, and bonding conditions. This development is expected to contribute to the fabrication of future flexible substrate stacking.

Processes of silver photodiffusion into Ge‐chalcogenide probed by neutron reflectivity technique

We performed time‐resolved neutron reflectivity measurement for stacks of Ag 500 Å/Ge25S75 1500 Å/Si substrate and Ge33S67 1500 Å/Ag 500 Å/Si substrate to clarify silver photodiffusion process into Ge‐chalcogenide layer. For Ag 500 Å/Ge25S75 1500 Å/Si substrate stack, it was found that the silver layer dissolves into Ge‐chalcogenide layer within 2 min by the light exposure, and Ag‐doped reaction layer forms. However, two‐layer structure with thicknesses of 800 and 1100 Å was established by a prolonged light exposure for 70 min and it did not change to form one homogeneous layer. For Ge33S67 1500 Å/Ag 500 Å/Si substrate stack, silver rapidly dissolves into Ge33S67layer leaving a thin silver layer in the first 2 min, and then, silver slowly dissolves from the silver layer as the next reaction process. At approximately 25 min light exposure, an anomalous decrease in the neutron reflectivity, suggesting a formation of macroscopic surface roughness, was observed.

Direct imaging of boron segregation at dislocations in B:diamond heteroepitaxial films.

A thin film of heavily B-doped diamond has been grown epitaxially by microwave plasma chemical vapor deposition on an undoped diamond layer, on top of a Ir/YSZ/Si(001) substrate stack, to study the boron segregation and boron environment at the dislocations present in the film. The density and nature of the dislocations were investigated by conventional and weak-beam dark-field transmission electron microscopy techniques, revealing the presence of two types of dislocations: edge and mixed-type 45° dislocations. The presence and distribution of B in the sample was studied using annular dark-field scanning transmission electron microscopy and spatially resolved electron energy-loss spectroscopy. Using these techniques, a segregation of B at the dislocations in the film is evidenced, which is shown to be intermittent along the dislocation. A single edge-type dislocation was selected to study the distribution of the boron surrounding the dislocation core. By imaging this defect at atomic resolution, the boron is revealed to segregate towards the tensile strain field surrounding the edge-type dislocations. An investigation of the fine structure of the B-K edge at the dislocation core shows that the boron is partially substitutionally incorporated into the diamond lattice and partially present in a lower coordination (sp(2)-like hybridization).