Parasitic Substrate Research Articles

Parasitic masking effect in GaN SA-MOVPE using SiO2 masks deposited by the PECVD technique

The paper reports a phenomenon of parasitic substrate masking during selective area metalorganic vapor phase epitaxy (SA-MOVPE) of gallium nitride (GaN) using silicon dioxide (SiO2) masks deposited by plasma enhanced chemical vapor deposition (PECVD) at pressures above 150 hPa. The discussion of the thermal stability and nitridation process of the SiO2 films is followed by the presentation of the experimental work results focused on the investigation of the relationship between the parasitic masking effect and pressure in the MOVPE reactor chamber. Analysis of the surface morphology is conducted using scanning electron microscopy (SEM) and atomic force microscopy (AFM). A hypothesis was proposed explaining the formation of the deposition-free region that indicates silanimine (HNSi) layer formation as a possible factor responsible for the adverse inhibition of GaN nucleation.

An Active EMI Cancellation Technique Achieving a 25-dB Reduction in Conducted EMI of LIN Drivers

Robustness to electromagnetic interference (EMI) is one of the primary design aspects of state of the art automotive ICs like System Basis Chips (SBCs) which provide a wide range of analog, power regulation and digital functions on the same die. One of the primary sources of conducted EMI on the Local Interconnect Network (LIN) driver output is an integrated switching DC-DC regulator noise coupling through the parasitic substrate capacitance of the SBC. In this paper an adaptive active EMI cancellation technique to cancel the switching noise of the DC-DC regulator on the LIN driver output to ensure electromagnetic compatibility (EMC) is presented. The proposed active EMI cancellation circuit synthesizes a phase synchronized cancellation pulse which is then injected onto the LIN driver output using an on-chip tunable capacitor array to cancel the switching noise injected via substrate. The proposed EMI reduction technique can track and cancel substrate noise independent of process technology and device parasitics, input voltage, duty cycle and loading conditions of the DC-DC switching regulator. The EMI cancellation system is designed and fabricated on a 180nm Bipolar-CMOS-DMOS (BCD) process with an integrated power stage of a DC-DC buck regulator at a switching frequency of 2MHz along with an automotive LIN driver. The EMI cancellation circuit occupies an area of 0.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , which is less than 3% of the overall area in a standard SBC and consumes 12.5 mW of power and achieves 25 dB reduction of conducted EMI in the LIN driver output’s power spectrum at the switching frequency and its harmonics.

Capillary force induced the sodium metal infusion in the Sn@HCNF scaffold: A mechanical flexible metallic battery

The practical exploitation of the sodium metallic anodes (SMA), especially in the energy-dense battery models, is impeded by the progressive reactivity of the sodium (Na) deposits in the aprotic electrolyte, which leads to the dynamic interfacial properties, Na cation depletion and parasitic substrate pulverization. Through the coaxial electrospinning technique, herein, we exquisitely engineer the spatial arrangement and Na affinity of a mechanical-flexible, lightweight (1.0 mg cm−2) SMA scaffold, in which the carbothermal reduced Sn nanocrystallines are homogeneously riveted within the hollow carbon nanofibers (Sn@HCNF). Subsequently, the capillary effect induces the molten Na infusion into the hollow fibers at the preset amount, which enables the Na15Sn4 alloy formation and simplifies the presodiation procedure. As the pre-infused Na–Sn@HCNF anode (0.5* Na excess) coupled with NaVPO4F cathode (∼8.6 mg cm−2) in a proof-of-concept full cell model (2 mA h), the gravimetric energy density of 311.44 W h kg−1 at the maximized power output of 1245.76 W kg−1 (calculations based on the electroactive materials), as well as the robust cycling (89.6% for 300 cycles) upon various geometric flexing states are simultaneously achieved. This capillary driving strategy provides a scalable, straightforward, site-specific presodiation approach, which encourages the facile prototyping of the mechanical-flexible metallic batteries.

Origin(s) of Anomalous Substrate Conduction in MOVPE-Grown GaN HEMTs on Highly Resistive Silicon.

The performance of transistors designed specifically for high-frequency applications is critically reliant upon the semi-insulating electrical properties of the substrate. The suspected formation of a conductive path for radio frequency (RF) signals in the highly resistive (HR) silicon substrate itself has been long held responsible for the suboptimal efficiency of as-grown GaN high electron mobility transistors (HEMTs) at higher operating frequencies. Here, we reveal that not one but two discrete channels distinguishable by their carrier type, spatial extent, and origin within the metal-organic vapor phase epitaxy (MOVPE) growth process participate in such parasitic substrate conduction. An n-type layer that forms first is uniformly distributed in the substrate, and it has a purely thermal origin. Alongside this, a p-type layer is localized on the substrate side of the AlN/Si interface and is induced by diffusion of group-III element of the metal-organic precursor. Fortunately, maintaining the sheet resistance of this p-type layer to high values (∼2000 Ω/□) seems feasible with particular durations of either organometallic precursor or ammonia gas predose of the Si surface, i.e., the intentional introduction of one chemical precursor just before nucleation. It is proposed that the mechanism behind the control actually relies on the formation of disordered AlSiN between the crystalline AlN nucleation layer and the crystalline silicon substrate.

AlInGaN/GaN HEMTs With High Johnson’s Figure-of-Merit on Low Resistivity Silicon Substrate

This work demonstrates high-performance AlInGaN/AlN/GaN high electron mobility transistors grown on 150 mm p-type low resistivity (resistivity~ 20-100 Ω-cm) silicon substrate with state-of-the-art Johnson's figure-of-merit (JFOM). Current gain cut-off frequency (fT) of 83 GHz and 63 GHz and power gain cut-off frequency (fmax) of 95 GHz and 77 GHz with a three-terminal off-state breakdown voltage of 69 V and 127 V, resulting in a high JFOM of 5.7 THz-V and 8.1 THz-V are achieved on the devices with a gate length of 0.16 μm and gate to drain distance of 2 μm and 4 μm, respectively. The fT and J-FOM are comparable or better than the reported values obtained on high resistivity silicon and SiC substrates for devices with similar gate length. On the other hand, GaN-on-Si HEMT structure on the LR-Si substrate exhibits lower power gain and power added efficiency due to strong capacitive coupling effects. TCAD large signal output power simulation indicates significant improvements in output power by minimizing the defects and free charge carriers in the GaN buffer even in the presence of the parasitic channel conduction and conductive silicon substrate. We further propose a modified equivalent circuit model of the parasitic conduction to take into account the conductivity of the GaN and AlGaN buffer.

Field Emission Air-Channel Devices as a Voltage Adder.

Field emission air-channel (FEAC) devices can work under atmospheric pressure with a low operation voltage when the electron channel is far less than the mean free path (MFP) in the air, thereby making them a practical component in circuits. Forward and reverse electron emissions of the current FEAC devices demonstrated symmetric Fowler–Nordheim (F–N) plots owing to the symmetric cathode and anode electrodes. This research aimed to demonstrate the arithmetic application of the FEAC devices, their substrate effect, and reliability. A voltage adder was composed of two FEAC devices whose two inputs were connected to two separate function generators, and one output was wire-connected to an oscilloscope. The devices were on a thin dielectric film and low-resistivity silicon substrate to evaluate the parasitic components and substrate effect, resulting in frequency-dependent impedance. The results show that the FEAC devices possessed arithmetic function, but the output voltage decreased. The FEAC devices were still capable of serving as a voltage adder after the reliability test, but electric current leakage increased. Finite element analysis indicated that the highest electrical fields and electron trajectories occur at the apices where the electrons travel with the shortest route less than the MFP in the air, thereby meeting the FEAC devices’ design. The modeling also showed that a sharp apex would generate a high electric field at the tip-gap-tip, enhancing the tunneling current.

(Invited) Integration of an Epitaxial-Base-Link HBT Device with fT = 300GHz, fmax 480GHz in 90nm CMOS

SiGe HBT based BiCMOS technologies have found widespread use in millimeter-Wave (mmW) applications such as high-speed communication and automotive radar, but are also receiving increased attention for operating frequencies above 100GHz. The drive for higher operating frequencies while reducing power consumption continues to fuel the development of new BiCMOS technologies with HBTs featuring higher switching speeds (fmax) integrated with smaller, more power efficient and cost effective CMOS nodes. There is strong evidence however, that in volume production double poly self-aligned (DPSA) HBT architectures may be limited to fmax of 400GHz[i],[ii],[iii],[iv],[v],[vi]. Alternative HBT architectures to overcome this limitation have been proposed[vii],[viii],[ix].In this paper we report the successful integration of a SiGe HBT module with fT = 300GHz, fmax = 480GHz in a 90nm BiCMOS technology platform. Building on previous studies by IHP[x] and Infineon[xi] the Epitaxial-Base-Link process flow was further adapted for compatibility to the 90nm CMOS base technology. The new technology platform features seven Cu metal layers high quality passives including a TaN resistor and a MiM capacitor positioned between metal levels 6 and 7 for low parasitic substrate coupling. One metal layer was added compared to the 130nm platform to facilitate the transition from thin wire to RF metallization.Figure 1 shows a TEM cross section of one of the first successful 90nm BiCMOS runs. Key challenges of the integration into the new CMOS node will be summarized in the presentation. The same device showed nearly ideal Gummel characteristics. CML ring oscillators with a design width EW of 190nm and 2.8 µm length achieved a wafer mean gate delay of 1.86ps with a standard deviation of 1.9%.Acknowledgment: This work was supported by the European Commission and the German Federal Ministry of Education and Research (BMBF) under project ref# 16ESE0202S ECSEL-TARANTO. [i] V. P. Trivedi et al., “A 90nm BiCMOS Technology featuring 400 GHz fMAX SiGe:C HBT”, in Bipolar / BiCMOS Circuits and Technology Meeting, 2016, pp. 60-63. [ii] V. Jain et al., “Device and circuit performance of SiGe HBTs in 130nm BiCMOS process with fT/fmax of 250/330GHz,” IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2014, pp. 96-99. [iii] P. Chevalier et al., “A 55 nm triple gate oxide 9 metal layers SiGe BiCMOS technology featuring 320 GHz fT / 370 GHz fMAX HBT and high-Q millimeter-wave passives,” in International Electron Devices Meeting (IEDM), 2014, pp. 3.9.1-3.9.3. [iv] J. Pekarik et al., “A 90nm SiGe BiCMOS technology for mm-wave and high-performance analog applications,” in IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2014, pp. 92–95. [v] P. Hurwitz, R. Kanawati, K. Moen, E. Preisler, S. Chaudhry and M. Racanelli, "Advances in RF foundry technology for wireless and wireline communications," 2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), Austin, TX, 2016, pp. 5-8. [vi] J. Böck et al., “SiGe HBT and BiCMOS process integration optimization within the DOTSEVEN project”, in Bipolar / BiCMOS Circuits and Technology Meeting, 2015, pp. 121-124. [vii] Q. Z. Liu et al, “SiGe HBTs in 90nm BiCMOS Technology demonstrating fT / fmax 285GHz / 475GHz through simultaneous reduction of base resistance and extrinsic collector capacitance”, ECS transactions, 64(6) , 2014, pp. 285 – 294. [viii] A. Fox, B. Heinemann, R. Barth, S. Marschmeyer, C. Wipf and Y. Yamamoto, "SiGe:C HBT architecture with epitaxial external base," 2011 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Atlanta, GA, 2011, pp. 70-73. [ix] V.T. Vu, D. Celi, T. Zimmer, S. Fregonese, P. Chevalier, “Advanced Si/SiGe HBT architecture for 28-nm FD-SOI BiCMOS”, in Bipolar / BiCMOS Circuits and Technology Meeting, 2016, pp. 64-67. [x] B. Heinemann et al., "SiGe HBT with fx/fmax of 505 GHz/720 GHz," 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2016, pp. 3.1.1-3.1.4. [xi] D. Manger et al., "Integration of SiGe HBT with fT=305 GHz, fmax=537GHz in 130nm and 90nm CMOS," 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), San Diego, CA, 2018, pp. 76-79. Figure 1

Accurate leakage current models for MOSFET nanoscale devices

This paper underlines a closed forms of MOSFET transistor’sleakage current mechanisms inthe sub 100nmparadigm.The incorporation of draininduced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage (Isub) wasinvestigated in detail. The Band-To-Band Tunneling (IBTBT) due to the source and Drain PN reverse junction were also modeled witha close and accurate model using a rectangularapproximation method (RJA). The three types of gate leakage (IG) were also modeled and analyzed for parasitic (IGO), inversion channel (IGC), and gate substrate (IGB).In addition, the leakage resources due to the aggressive reduction in the oxide thickness (&lt;5nm) have been investigated. Simulation results using HSPICEexhibits a tremendous agreement with the BSIM4 model. The dominant value of the sub-threshold leakage was due to the DIBL and GIDL effects. Various recommendations regarding minimizing the leakage current at both device level and the circuit level were suggested at the end of this paper

Suppression of substrate mode in GaN-based green laser diodes.

Parasitic substrate mode readily appears in GaN-based laser diodes (LDs) because of insufficient optical confinement, especially for green LDs. Substrate modes affect the behavior of a LD severely, including the laser beam quality, the optical output power, the longitudinal mode stability, and the maximum modulation speed. In this article, systematic studies on the n-cladding layer (CL) design to suppress the substrate mode of GaN-based green LDs were carried out. We established a contour map to describe the relationship between the optical confinement (determined by the thickness and the refractive index) of n-CL and the substrate mode intensity by simulating the near-field pattern and the far-field pattern. We found that it was difficult to obtain the Gaussian-shape far-field pattern using AlGaN as a cladding layer due to the appearance of cracks induced by tensile strain. However, this can be realized by introducing quaternary AlInGaN as a cladding layer since refractive index and strain can be tuned separately for quaternary alloy.

Electrical modeling of tapered TSV including MOS-Field effect and substrate parasitics: Analysis and application

In this paper, a simple closed-form model identifying the electrical behavior of a taper through silicon via (TSV) is reported. The model is based on the Transmission Line Method (TLM) and 3D electromagnetic simulations. The usefulness of the modeling approach is validated through measurements on some test structures over a wide range of frequencies from DC to 10 ​GHz. The substrate coupling and MOS effects are included in the electrical description of the 3D system as they are no longer negligible at high-frequency range operation. The efficient 3D-TLE (Transmission Line Extractor) by INL (Institute of Nanotechnology of Lyon) tool is used to extract the impedance of contacts and TSVs. Moreover, as an application of this extractor, a 26GHz/2 ​GHz bandwidth TSV based RF filter is proposed and designed.

Modeling of Advanced RF Bulk FinFETs

The modeling of the advanced RF bulk FinFETs is presented in this letter. Extensive S-parameter measurements, performed on the advanced RF bulk FinFETs, show 31% improvement in cutoff frequency over recent work [1] . The transistor’s characteristics are dominated by substrate parasitics at intermediate frequencies (0.1–10 GHz) and gate parasitics at high frequencies (above 10 GHz). The Berkeley short-channel IGFET model-common multi gate model is improved to account for the impact of substrate coupling on the RF parameters. The model demonstrates excellent agreement with the measured data over a broad range of frequencies. The model passes AC, DC and RF symmetry tests, demonstrating its readiness for (RF) circuit design using FinFETs.

Sensitivity analysis and uncertainty estimation for nanoscale MOSFET

AbstractAnalytical expressions of the sensitivity analysis and uncertainty estimation for intrinsic elements and substrate parasitics in the small‐signal equivalent circuit model of metal‐oxide‐semiconductor field‐effect transistor, related to the S‐parameter measurement uncertainties, are derived in this paper. And the substrate parasitic elements are extracted, and corresponding sensitivities are calculated by using a cut‐off condition extraction procedure. Furthermore, the intrinsic model parameters and their uncertainties versus bias voltage are also investigated to give more reliable extraction results suitable for implementation in automatic multibias extraction programs.

An investigation of the DC and RF performance of InP DHBTs transferred to RF CMOS wafer substrate * * Project supported by the National Natural Science Foundation of China (No. 61331006) and the Natural Science Foundation of Zhejiang Province (No. Y14F010017).

This paper investigated the DC and RF performance of the InP double heterojunction bipolar transistors (DHBTs) transferred to RF CMOS wafer substrate. The measurement results show that the maximum values of the DC current gain of a substrate transferred device had one emitter finger, of 0.8 μm in width and 5 μm in length, are changed unobviously, while the cut-off frequency and the maximum oscillation frequency are decreased from 220 to 171 GHz and from 204 to 154 GHz, respectively. In order to have a detailed insight on the degradation of the RF performance, small-signal models for the InP DHBT before and after substrate transferred are presented and comparably extracted. The extracted results show that the degradation of the RF performance of the device transferred to RF CMOS wafer substrate are mainly caused by the additional introduced substrate parasitics and the increase of the capacitive parasitics induced by the substrate transfer process itself.

Characterisation of a novel reverse-biased PPD CMOS image sensor

A new pinned photodiode (PPD) CMOS image sensor (CIS) has been developed and characterised. The sensor can be fully depleted by means of reverse bias applied to the substrate, and the principle of operation is applicable to very thick sensitive volumes. Additional n-type implants under the pixel p-wells, called Deep Depletion Extension (DDE), have been added in order to eliminate the large parasitic substrate current that would otherwise be present in a normal device. The first prototype has been manufactured on a 18 μm thick, 1000 Ω .cm epitaxial silicon wafers using 180 nm PPD image sensor process at TowerJazz Semiconductor. The chip contains arrays of 10 μm and 5.4 μm pixels, with variations of the shape, size and the depth of the DDE implant. Back-side illuminated (BSI) devices were manufactured in collaboration with Teledyne e2v, and characterised together with the front-side illuminated (FSI) variants. The presented results show that the devices could be reverse-biased without parasitic leakage currents, in good agreement with simulations. The new 10 μm pixels in both BSI and FSI variants exhibit nearly identical photo response to the reference non-modified pixels, as characterised with the photon transfer curve. Different techniques were used to measure the depletion depth in FSI and BSI chips, and the results are consistent with the expected full depletion.

Switched Substrate-Shield-Based Low-Loss CMOS Inductors for Wide Tuning Range VCOs

A switched substrate-shield inductor (SSI) topology in bulk CMOS is proposed which minimizes parasitic capacitance and substrate losses, while tuned magnetically induced currents facilitate inductor tunability. The high frequency behavior of the induced current is analyzed, resulting in intuitive insights and design guidelines for a high-performance SSI. An SSI prototype in 65-nm bulk CMOS achieves 34% inductance tunability with a quality factor of >10.3. A voltage-controlled oscillator (VCO) using SSI achieves 40.3% tuning range, from 21 to 31.6 GHz, and a phase noise of −119.1 ± 3.7 dBc/Hz at 10-MHz offset frequencies. The VCO core consumes 4.3 ± 0.2 mW from a 1-V supply.

Fully Depleted Pinned Photodiode CMOS Image Sensor With Reverse Substrate Bias

A new pixel design using fully depleted pinned photodiode (PPD) in a 180-nm CMOS image sensor (CIS) process has been developed and the first experimental results from a test chip are presented. The sensor can be fully depleted by means of reverse bias applied to the substrate, and the principle of operation is applicable to very thick sensitive volumes. Additional n-type implants under the in-pixel p-wells have been added to the manufacturing process in order to eliminate the large parasitic substrate current that would otherwise be present in a normal device. The new design shows the same electro-optical performance as the PPD pixel it is based on, and can be fully depleted without significant leakage currents. This development has the potential to greatly increase the quantum efficiency of scientific PPD CIS at near-infrared and soft X-ray wavelengths.

Free-space terahertz radiation from a LT-GaAs-on-quartz large-area photoconductive emitter.

We report on large-area photoconductive terahertz (THz) emitters with a low-temperature-grown GaAs (LT-GaAs) active layer fabricated on quartz substrates using a lift-off transfer process. These devices are compared to the same LT-GaAs emitters when fabricated on the growth substrate. We find that the transferred devices show higher optical-to-THz conversion efficiencies and significantly larger breakdown fields, which we attribute to reduced parasitic current in the substrate. Through these improvements, we demonstrate a factor of ~8 increase in emitted THz field strength at the maximum operating voltage. In addition we find improved performance when these devices are used for photoconductive detection, which we explain through a combination of reduced parasitic substrate currents and reduced space-charge build-up in the device.

Above 2000 V breakdown voltage at 600 K GaN-on-silicon high electron mobility transistors

We report a three-terminal breakdown voltage over 3 kV on AlGaN/GaN high electron mobility transistors (HEMTs) grown on 6-in. silicon (111) substrate with a buffer thickness of 5.5 μm. A local substrate removal all around the drain of the transistors has been developed in order to suppress the parasitic substrate conduction, which enables improving the device breakdown voltage by more than 200%. This establishes a new record breakdown voltage for GaN-on-silicon lateral power devices while maintaining a low-specific on-resistance of about 10 m Ω cm2. Furthermore, the device performance has been investigated at elevated temperature up to 600 K under high vacuum. Breakdown voltages well above 2 kV at temperatures exceeding 300 °C have been achieved for the first time owing to the suppression of the buffer layer/Silicon substrate parasitic conduction. These data demonstrates that the local substrate removal is not only an efficient solution to significantly boost the device breakdown voltage but also allows improving the high voltage operation under high temperature, which is a key feature for high power electronic applications.

Consistent Modeling and Power Gain Analysis of Microwave SiGe HBTs in CE and CB Configurations

This paper presents a methodology to model SiGe HBTs biased in common-emitter and in common-base configurations including the bias-dependent substrate parasitics, which allows determining the more suitable configuration to achieve maximum power gain at different frequency ranges. Model–experiment correlations up to 100 GHz for different bias conditions verify the validity of the proposed circuit representations using the same values for the parameters in both configurations.

Microstrip Antenna Pattern Reconfiguration Using On-Chip Parasitic Elements

In this paper, a design of pattern reconfigurable microstrip patch antenna and its simulation using CSTMW simulator is presented. The designed antenna is also fabricated and tested. The design consists of microstrip patch printed on FR-4 substrate with a coaxial line feeding on the back of the antenna which is the active element. Two on-chip parasitic elements (OCPE) also are printed on FR-4 substrate, each of which connected through a via hole to the ground. The proposed design has the advantage of movable parasitic chip elements with the same motherboard to control the reconfigurable pattern direction as well as operating frequency. It is also have the advantages of parasitic elements rotation to fit reception/transmission required steering angle. The results obtained show that the steering angle of the main beam in the H-plane depends upon the dimension of the parasitic element substrate as well as the type of the patch antenna. The presented antenna is suitable for different application, including Wifi and WiMax systems.