Substrate Parasitic Effects Research Articles

The impact of total ionizing dose on RF performance of 130 nm PD SOI I/O nMOSFETs

In this paper, the degradation mechanism of RF performance of 130 nm T-gate partially depleted (PD) silicon-on-insulator input-output nMOSFETs at different total ionizing dose levels has been investigated. RF figures of merit (the cut-off frequency fT, maximum oscillation frequency fmax) show significant degradation, about 26% and 80% respectively. The variation of the small signal parameters (output conductance (gds), transconductance (gm), gate resistance (Rg) and capacitance (Cgg)) at different TID levels has been discussed. TID-induced trapped charges at gate oxide and STI corner increase the vertical electric field, which leads to the broadening of depletion layer and the narrowing of neutral body region. Furthermore, the small signal parameters appear more complex degradation in the wide frequency range. A model which considers the body and substrate parasitic effects is presented, and the results of ADS simulation based on this model are consistent with the experimental results.

Analysis of the Failure and Performance Variation Mechanism of MEMS Suspended Inductors with Auxiliary Pillars under High-g Shock.

Microelectromechanical systems (MEMS) suspended inductors have excellent radio frequency (RF) performance and they are compatible with integrated circuit (IC). They will be shocked during manufacturing, transportation, and operation; in some applications, the shock amplitude can be as high as tens of thousands of gravitational acceleration (g, 9.8 m/s2). High-g shock will lead to the inductor deformation which affects its performance or even failure of the inductor structure. However, few studies have been carried out on the inductors under high-g shock. In this study, a kind of MEMS suspended inductor with excellent RF and mechanical performance is designed and fabricated. The failure and performance variation mechanism of the inductor under high-g shock is analyzed by measuring and comparing the performance measurement results and the π model parameters extraction results of the inductors before and after air cannon shock test. The results show that the increase of energy loss caused by substrate parasitic effect and the properties variation of the coil material affected by high-g shock are the main reasons for the decrease of RF performance parameters, and the critical stress exceeding the interlayer adhesion is the main reason for the failure of the inductor.

A Novel Empirical Model for CMOS Schottky Diodes up to 67 GHz

A novel empirical model capable of predicting dc current and RF capacitance characteristics for CMOS Schottky diodes is first proposed. The model is developed upon a physical-based equivalent circuit and a set of closed-form formulas. Different current transport mechanisms including thermionic emission, tunneling, and carrier velocity saturation are counted by nonlinear resistances in the intrinsic model, while stray and substrate parasitic effects are also included in the parasitic model. A systematic procedure is built up to directly extract all the model parameters from measurements. The model is validated in 65- and 130-nm CMOS technology, and the modeled results show an excellent agreement with the measured data up to 67 GHz, which is the highest modeling frequency reported up till now.

Analysis of the Performance Variation Mechanism of MEMS Suspended Inductors under Mechanical Shock.

Micro-electromechanical system (MEMS) suspended inductors have been widely studied in recent decades because of their excellent radio frequency performance. However, the deformation of the inductor coil and the performance variation usually occur to the MEMS suspended inductors when the inductors are under mechanical shock. Few studies have been carried out on the performance variation of MEMS suspended inductors under shock. In this study, the mechanism of the performance variation of MEMS suspended inductors under mechanical shock is analyzed by combining theoretical analysis and experiments. A theoretical analysis based on the lumped-element equivalent model is presented and shock tests are carried out. The shock tests show that the main reason of the MEMS suspended inductor performance variation after mechanical shock is the variation of the substrate parasitic effect, which is caused by the variation of the suspension height of the inductor after shock. The test results agree with the theoretical analysis.

Design, Fabrication, and Characterization of Package Embedded Solenoidal Magnetic Core Inductors for High-Efficiency System-In-Package Integrated Voltage Regulators

In this paper, we discuss the design, fabrication, and characterization of package embedded solenoidal inductor using a NiZn ferrite magnetic core material based on the novel fabrication process. The process relies on stencil printing of the magnetic core material along with the photolithography and copper electroplating of the inductor’s traces. The electrical parameters of the fabricated inductors were extracted using a pi-equivalent circuit and showed an average dc resistance of 29 $\text{m}\Omega $ , an inductance of 26 nH, and an ac resistance of $2.62~\Omega $ at 100 MHz, which represents the targeted switching frequency of the system-in-package integrated voltage regulator. The organic substrate parasitic effects were accounted for through the extraction of an average shunt capacitance of 1.2 pF and an average parasitic conductance of 0.12 mS at 100 MHz. The measured 10% saturation current of the inductor was 9.6 A. The electrical parameters of the fabricated inductors were modeled and showed a good agreement with the measured data.

Magnetic Core Solenoid Power Inductors on Organic Substrate for System-in-Package Integrated High-Frequency Voltage Regulators

In this paper, the design, modeling, fabrication, and characterization of System-in-Package (SiP) solenoid power inductor using a NiZn ferrite composite magnetic core material is demonstrated. A novel fabrication process has been developed for integrating the inductor into the buck-type integrated voltage regulator (IVR) module. The process uses stencil printing to deposit and pattern the magnetic core material. Photolithography and copper electroplating are used to form the windings. The electrical parameters of the fabricated inductors were extracted from measurements. The inductors had an average dc resistance of 19 $\text{m}\Omega $ , average inductance of 28.3 nH, and average ac resistance of $2.28~\Omega $ at 100 MHz, which is the operating frequency of the IVR. The organic substrate parasitic effect led to an average shunt capacitance of 2.31 pF and an average parasitic conductance of 0.12 mS at 100 MHz. The 10% saturation current was 11.53 A. The electrical parameters of the fabricated inductors were modeled and showed good accuracy with measured data. The inductors showed an inductance to dc resistance ratio of 1613 nH/ $\Omega $ . The area and volume energy densities were 158.4 nJ/mm2 and 283.0 nJ/mm3, respectively. These are the highest reported values for a solenoid magnetic core power inductor at 100 MHz.

Observation of nonconservation characteristics of radio frequency noise mechanism of 40-nm n-MOSFET**Project supported by the National Natural Science Foundation of China (Grant No. 69901003) and the Scientific Research Fund of Sichuan Provincial Education Department.

Bias non-conservation characteristics of radio-frequency noise mechanism of 40-nm n-MOSFET are observed by modeling and measuring its drain current noise. A compact model for the drain current noise of 40-nm MOSFET is proposed through the noise analysis. This model fully describes three kinds of main physical sources that determine the noise mechanism of 40-nm MOSFET, i.e., intrinsic drain current noise, thermal noise induced by the gate parasitic resistance, and coupling thermal noise induced by substrate parasitic effect. The accuracy of the proposed model is verified by noise measurements, and the intrinsic drain current noise is proved to be the suppressed shot noise, and with the decrease of the gate voltage, the suppressed degree gradually decreases until it vanishes. The most important findings of the bias non-conservative nature of noise mechanism of 40-nm n-MOSFET are as follows. (i) In the strong inversion region, the suppressed shot noise is weakly affected by the thermal noise of gate parasitic resistance. Therefore, one can empirically model the channel excess noise as being like the suppressed shot noise. (ii) In the middle inversion region, it is almost full of shot noise. (iii) In the weak inversion region, the thermal noise is strongly frequency-dependent, which is almost controlled by the capacitive coupling of substrate parasitic resistance. Measurement results over a wide temperature range demonstrate that the thermal noise of 40-nm n-MOSFET exists in a region from the weak to strong inversion, contrary to the predictions of suppressed shot noise model only suitable for the strong inversion and middle inversion region. These new findings of the noise mechanism of 40-nm n-MOSFET are very beneficial for its applications in ultra low-voltage and low-power RF, such as novel device electronic structure optimization, integrated circuit design and process technology evaluation.

An investigation on capacitance-trigger ESD protection devices for high voltage integrated circuits

A novel cascaded complementary dual-directional silicon controlled rectifier (CCDSCR) structure has been proposed and implemented in a 0.5μm 20V Bipolar/CMOS/DMOS process as an ESD (electrostatic discharge) protection device. The ESD characteristics of the capacitance-trigger CCDSCR has been investigated by transmission line pulse (TLP) testing. Compared with the substrate-trigger insulated gate bipolar transistor with the enhanced substrate parasitic capacitance, the gate-driven trigger insulated gate bipolar transistor with the gate coupling capacitance and the normal dual-directional silicon controlled rectifier, the CCDSCR has the highest holding voltage of about 25.4V and the best current conduction uniformity. In addition, it has the best figure of merit (FOM) with the value of about 0.64mA/μm2. The good current conduction uniformity in CCDSCR due to the enhanced substrate parasitic capacitance-trigger effect is finally confirmed by Sentaurus simulations.

Analytical study of substrate parasitic effects in common-base and common-emitter SiGe BHT amplifiers

An analytical study to quantify the substrate parasitic effects on SiGe HBT amplifiers in both common-base and common-emitter configuration is presented. The power gain relations and stability factors are derived from the modelled S-parameters which are computed at a fixed bias point from the small-signal hybrid-∏ model of SiGe HBT in both configurations. It has been shown that the power gains of SiGe HBT amplifiers in both configurations are degraded when extrinsic and substrate parasitics are taken into account. The degradation in power gains is found to be more pronounced for CB configuration, which makes the design of HBT amplifiers, particularly in the CB mode, difficult. Close matching of the modelled data with the reported experimental results validates the proposed methodology.

Power Gain Characteristics of RF MOSFETs under Different Configurations

The power gain characteristics of MOSFET under common-source (CS) and common-gate (CG) configurations are analytically studied and verified with simulations using RF MOSFET large- signal models. The substrate parasitic effects on the power gain characteristics are also investigated. While little impact is observed on the CS power gain characteristics due to substrate parasitics, the power gain characteristics of the CG configuration are greatly and adversely influenced. High- frequency power-gain characteristics can be improved for the CG configuration with reduced substrate effects and lowered gate resistance values. The power gain potential of CG configuration could be eventually realized by using high- resistivity or SOI substrate and gate stacks of lower resistance.

Accurate substrate modelling of RF CMOS

The losses within the substrate of an RF IC can have significant effect on performance in a mixed signal application. In order to model substrate coupling accurately, it is represented by an RC network to account for both resistive and dielectric losses at high frequency (> 1 GHz). A small-signal equivalent circuit model of an RF IC inclusive of substrate parasitic effect is analysed in terms of its y-parameters and an extraction procedure for substrate parameters has been developed. By coupling the extracted substrate parameters along with extrinsic resistances associated with gate, source and drain, a standard BSIM3 model has been extended for RF applications. The new model exhibits a significant improvement in prediction of output reflection coefficient S22 in the frequency range from 1 to 10 GHz in device mode of operation and for a low noise amplifier (LNA) at 2.4 GHz. Copyright © 2006 John Wiley & Sons, Ltd.

A simple lumped electrical model for an RF MEMS switch considering lossy substrate effects

This work focuses on electrostatically actuated micro-electro-mechanical systems (MEMS) capacitive switches, intended for adaptive output stage of power amplifiers. These devices are particularly attractive because theoretically they are capable of very high quality factor values due to the air gap between plates and the low resistivity of lines and bridge. On the other hand, substrate parasitic effects, overlooked up to date, can seriously impair device performance. In this paper, we introduce a lumped element equivalent circuit taking into account substrate effects. Model validation is based on measurements carried out in the 50 MHz–40 GHz range.

Substrate Leakage Current in InGaP/GaAs Heterojunction Bipolar Transistors

Substrate leakage current in InGaP/GaAs heterojunction bipolar transistors (HBTs) has been observed. For a substrate thickness of 100 µm and an emitter area of 60 µm2, the parasitic current is on the order of 10-8 A. The current flowing between the collector terminal and the substrate can be decomposed into linear and parabolic components. The parabolic dependence is also observed in Medici simulation. A theoretical derivation based on electron drift in the substrate shows parabolic dependence on applied voltage, consistent with our measurement and Medici simulation. In addition, it has been found that the current is inversely proportional to the cube of substrate thickness. To account for this substrate parasitic effect, a modification of the vertical bipolar inter-company (VBIC) model is proposed.