Substrate Noise Research Articles

Identification of semen traces at a crime scene through Raman spectroscopy and machine learning

Biological fluid stains can be instrumental in solving crimes. Identification of semen can help reconstruct events in sexual assault cases and identify suspects via DNA profiling. Current methods for semen identification suffer from limitations, including destruction of the sample and potential false positives. One of the main unsolved issues is the elimination of underlying substrate interference. In this paper, chemometric approaches were developed to isolate and identify a biofluid stain on interfering substrates using Raman spectroscopy. The first approach, called Multivariate Curve Resolution with the Addition Method, combines the standard addition method with multivariate curve resolution. The second one uses a criterion based on reducing the spectrum complexity when a spectral component is removed from a Raman spectrum of a multi-component sample entirely. The results demonstrate the superiority of the first approach relative to the second for both small volume fraction of the fluid stain compared to the substrate and random noise.

Adjusting the surface quality of printed components via controlling dispersant content to improve the electrical performance of DLP-printed PZT ceramics and devices

This paper aims to enhance the surface quality of digital light processing (DLP) printed lead zirconate titanate (PZT) components by controlling the content of BYK-111 dispersant, thereby improving the electrical properties of the resulting printed piezoelectric ceramics and devices. 55 vol% high solid loading PZT slurries with different dispersant contents were prepared and assessed for their dispersion stability, rheological behavior and curing characteristics. The slurry containing 1 wt% BYK-111 demonstrated ideal rheological properties, notably achieving a low viscosity of 1.37 Pa·s at 100 s−1. The surface roughness of the printed ceramic component was reduced to 69.3 nm, representing a 57.1 % improvement in surface quality compared to other dispersant levels. The printed PZT ceramic exhibited superior piezoelectric performance, with a piezoelectric constant d33 reaching 445 pC/N, surpassing most existing 3D-printed macro-sized piezoelectric ceramics. Furthermore, a DLP-printed 1–3 piezoelectric array was encapsulated to fabricate an acoustic emission (AE) sensor, which achieved a low substrate noise level of 31 dB and a high signal-to-noise ratio of 62 dB, outperforming commercial sensors. The optimal BYK-111 content not only ensures favorable dispersion stability and rheological properties in the slurry, but also significantly enhances the surface quality and density of the printed ceramic components, ultimately leading to the production of high-performance piezoelectric ceramics and devices.

Comparative experimental study of different fetch distances, interpolation algorithms, source substrate noise, sampling point counts, and resolution for NF of BDFA

Noise figure (NF) is a key metric for Fiber amplifier (FA), which affects the performance of signal transmission. The main factors affecting the NF are related to the amplified spontaneous emission (ASE) characteristics of the active fiber itself. However, during our study of NF, we found some easily overlooked factors that can have a significant impact on the results, such as the fetch distances and interpolation algorithm for calculating the ASE where the signal wavelength is located. Further, to date, we have also found little relevant research on whether the sampling characteristics of the instrument and the substrate noise contribute to the NF. On the other hand, bismuth-doped fiber amplifiers (BDFA) have developed rapidly in recent years. In this work, we use BDFA as an example, using different fetch distances, interpolation algorithms, substrate noise, and sampling variables (resolution and point counts), to comprehensively compare and analyze the impact caused by NF. The experimental results suggest that the distance between the sampling locations on either side of the signal and the center wavelength must exceed the signal’s bandwidth to obtain the actual NF; Linear interpolation and cubic interpolation are more suitable for calculating the NF; Even using a high power input signal of 0 dBm, the NF is only degraded by about 1.8% compared to the case where the substrate noise is ignored; In addition, the effect of different sampling point counts and resolutions have less influence on the NF. We believe this work provides a reliable reference value for calculating the accuracy of NF and will be useful for practical applications of active-fiber amplifiers.

Development of the matched filtration of a blurred digital image using its typical form

The appearance of "blurred" digital images is a consequence of the violation of the immobility of the camera during the shooting of the objects under study. To this end, a procedure was devised for matched filtering of the blurred digital image of the object using its typical image form in a series of frames. This procedure is based on the automated formation of a typical form of a digital image, as well as on the choice of special parameters for the transfer function of the matched filter. Adapting the procedure specifically to the typical form makes it possible to perform a more accurate assessment of the required parameters of the blurred digital image compared to the analytically set profile. The formation of a typical form makes it possible to take into account the features of the very formation of the blurred image on each frame of the original series. Based on this, a more accurate assessment of the initial approximation of the parameters of all Gaussians of the object image is performed. In practice, matched filtering makes it possible to highlight blurred images of objects against the background of substrate noise. Also, using the matched filtering procedure makes it possible to improve the segmentation of images of reference objects and reduce the number of false detections. The devised procedure for the matched filtering of a blurred digital image using its typical form has been tested in practice as part of the research in the framework of the CoLiTec project. It was implemented in the intraframe processing unit of the Lemur software for the automated detection of new and tracking of known objects. Owing to the use of Lemur software and the proposed computational procedure introduced into it, more than 700,000 measurements of various objects under study were successfully processed and identified

Substrate noise evaluation for lightly doped 45nm N-MOSFET using physical simulation models

ABSTRACT Analyzing substrate noise for an n-channel MOSFET (NMOS) substrate has been developed using various concepts such as virtual separation concept, p-contact to p-contact model and transistor switching noise model. A design is necessary for the substrate design development to minimize noise in FoMs (Figure Of Merits) and reduce threshold voltage developed noise. In the proposed model, a substrate-induced chip used for finding the noise in drain current has been improved with the increased doping density of an NMOS device. From a substrate noise coupling network with the proposed low signal equivalent circuit, the system measures noise at NMOS substrate using a hot carrier injection model. The proposed concept has been implemented in TCAD-SILVACO software, the design was made in ATHENA, and its corresponding electrical characteristics are simulated by the ATLAS software tool. This model extracts parameters such as overall noise in FoMs, drain current-gate current bias analysis, cross-correlation, and minimized threshold value. After capacitive coupling is achieved over different operation conditions and dimensions, excellent output is from simulated noise data.

Development of computational method for matched filtration with analytical profile of the blurred digital image

A computational method for matched filtration with analytical profile of the blurred digital image of the investigated objects on digital frames has been developed. Such «blurred» objects can be the result of an involuntary shift of a fixed camera, an incorrect choice of the mode of guiding the telescope (diurnal or object tracking) or a failure of the diurnal tracking. This computational method is based on the analytical selection of the typical form of the object’s image, as well as on the choice of special parameters for the transfer function of the matched filter for the blurred digital image, which makes it possible to evaluate the required parameters of the blurred digital image. In addition, determining the number of Gaussians of the object’s image makes it possible to perform the most accurate assessment of the initial approximation of the parameters of their shape. Thus, matched filtration makes it possible to highlight the investigated objects with a blurred image of a typical shape against the background of substrate noise. Using the computational method of matched filtration makes it possible to improve the segmentation of images of reference objects on the frame and reduce the number of false detections. The developed computational method for matched filtration with analytical profile of the blurred digital image of the investigated objects on the frames was tested in practice as part of the research of the CoLiTec project. It was implemented in the intraframe processing unit of the Lemur software for the operational automated detection of new and observation of known objects with a weak brightness. Owing to the Lemur software using and the proposed computational method introduced into it, more than 500,000 measurements of the various investigated objects were successfully processed and identified.

20 GHz substrate crosstalk sensor for mobile communication applications

ABSTRACT A 20 GHz substrate crosstalk noise sensor is presented. It is based on CMOS inverters used as analog amplifiers, in a Cherry-Hooper configuration. A buffer in the feedback path is employed to further enhance the circuit performance. The proposed substrate noise sensor is targeted to high-frequency mobile communication System-on-Chip applications for capturing the high-frequency inter-modulated coupling products through substrate. Superior sensing characteristics are demonstrated via simulation in an RFCMOS 65 nm process. The proposed design is capable of providing a gain of 6.6 dB over a frequency range from 8.5 MHz to 20 GHz with −1 dB compression point equal to 100 mV.

Heterogeneous and Monolithic 3D Integration Technology for Mixed-Signal ICs

For next-generation system-on-chips (SoCs) in diverse applications (RF, sensor, display, etc.) which require high-performance, small form factors, and low power consumption, heterogeneous and monolithic 3D (M3D) integration employing advanced Si CMOS technology has been intriguing. To realize the M3D-based systems, it is important to take into account the relationship between the top and bottom devices in terms of thermal budget, electrical coupling, and operability when using different materials and various processes during integration and sequential fabrication. In this paper, from this perspective, we present our recent progress of III-V devices on Si bottom devices/circuits for providing informative guidelines in RF and imaging devices. Successful fabrication of the high-performance InGaAs high electron mobility transistors (HEMTs) on the bottom ICs, with a high unity current gain cutoff frequency (fT) and unity power gain cutoff frequency (fMAX) was accomplished without substrate noise. Furthermore, the insertion of an intermediate metal plate between the top and bottom devices reduced the thermal interaction. Furthermore, the InGaAs photodetectors (PDs) were monolithically integrated on Si bottom devices without thermal damage due to low process temperature. Based on the integrated devices, we successfully evaluated the device scalability using sequential fabrication and basic readout functions of integrated circuits.

An Active EMI Cancellation Technique Achieving a 25-dB Reduction in Conducted EMI of LIN Drivers

Robustness to electromagnetic interference (EMI) is one of the primary design aspects of state of the art automotive ICs like System Basis Chips (SBCs) which provide a wide range of analog, power regulation and digital functions on the same die. One of the primary sources of conducted EMI on the Local Interconnect Network (LIN) driver output is an integrated switching DC-DC regulator noise coupling through the parasitic substrate capacitance of the SBC. In this paper an adaptive active EMI cancellation technique to cancel the switching noise of the DC-DC regulator on the LIN driver output to ensure electromagnetic compatibility (EMC) is presented. The proposed active EMI cancellation circuit synthesizes a phase synchronized cancellation pulse which is then injected onto the LIN driver output using an on-chip tunable capacitor array to cancel the switching noise injected via substrate. The proposed EMI reduction technique can track and cancel substrate noise independent of process technology and device parasitics, input voltage, duty cycle and loading conditions of the DC-DC switching regulator. The EMI cancellation system is designed and fabricated on a 180nm Bipolar-CMOS-DMOS (BCD) process with an integrated power stage of a DC-DC buck regulator at a switching frequency of 2MHz along with an automotive LIN driver. The EMI cancellation circuit occupies an area of 0.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , which is less than 3% of the overall area in a standard SBC and consumes 12.5 mW of power and achieves 25 dB reduction of conducted EMI in the LIN driver output’s power spectrum at the switching frequency and its harmonics.

System on Chip Noise Integrity Simulation

In mixed-signal integrated circuits, interference between digital noisy and sensitive analog/RF circuits is a challenging performance issue. The high cost of chip fabrication requires accurate simulation of the circuits’ performance versus signal and noise integrity. In this paper, a substrate crosstalk noise analysis flow is described and the characteristics of the substrate noise coupling mechanism are analyzed. The proposed noise integrity aware simulation flow properly estimates the substrate coupling effect and predicts the analog/RF victim circuit performance degradation due to noise coupling mechanisms. The methodology is implemented seamlessly in the current standard virtuoso-based design suite and is used in parallel with any commercial design tool, compatible with the standard analog/RF simulation process. The efficiency of the proposed methodology is validated by a full substrate crosstalk aware system on chip vehicle, designed in an RFCMOS 65 nm process. Silicon substrate, interconnect parasitics and package parasitics are efficiently modeled so as to enable the substrate noise simulation. A substrate crosstalk system on chip vehicle is designed in a 65 nm RFCMOS. The crosstalk noise victim is a 5 GHz CMOS LNA and the noise aggressor is a 90 kGates digital logic. It is demonstrated that by applying the proposed methodology, substrate crosstalk performance degradation can be efficiently captured. The LNA carrier degradation and the spectrum distortion re efficiently simulated by identifying all of the noise spurs propagating through the common silicon substrate from the digital logic to the custom low noise amplifier noise victim. The respective inter-modulation spurs are also captured.

A Variation Aware Jitter Estimation Methodology in ROs Considering Over/Undershoots in NTV Regime

A time-domain jitter estimation methodology considering process-voltage-temperature (PVT) variations of the single-ended ring oscillator (SERO) at an early stage of design is presented for near-threshold voltage (NTV) regime where nonlinearities dominates. For the first time, the model accounts for the jitter due to the over/undershoot region which is critical in the NTV regime. Further, the model uses effective drive current, Ieff model. The Ieff is obtained considering the regions of device operation, instead of using only saturation current for jitter calculation. A time-domain jitter model is developed by considering the change in transition threshold points (TTPs) whose relative values are supply independent and Ieff of each region with the PVT variation, design parameters, and with the introduction of noise in the circuit. The model analyzes the effects of random (white noise) and deterministic (supply, substrate) noise in the NTV regime. This approach is physics/topologybased and is valid for different technologies. Post-layout simulations have been performed on parasitic extracted netlist using CADENCE and HSPICE in STM 65nm CMOS Process Design Kit (PDK) to validate the jitter model in the NTV regime.

Impact of single event transient effect on adiabatic logic circuits

The evolution of the modern Complementary Metal Oxide Semiconductor technology has led to the scaling of the transistor size to nanometers. This has resulted in significant benefits to integrated circuits, such as higher speed, smaller circuit size and lower operating voltage. However, this smaller size and lower operating voltage have become highly susceptible to operational disturbances such as signal coupling, substrate noise, and single event effects caused by ionizing particles. Single Event Transient occurs when a high-energy particle strikes a combinational logic circuit. The charge deposited by the particle causes a transient voltage disturbance to load incorrect data. In this work, the impact of Single Event Transient on total power dissipation and the delay of static complementary logic is analyzed. Different circuits like basic inverter, adiabatic inverter, chain of inverters of complementary and adiabatic logic have been selected for the analysis. The technology node used for this analysis is 180 nm and 90 nm using Cadence Virtuoso. The result shows that on scaling, the effect of Single Event Transient is increased, and the use of an adiabatic logic reduces the power by 15% compared to conventional static logic circuits.

High frequency RFCMOS substrate noise sensor

A substrate crosstalk sensor featuring high performance gain over a wide frequency range is proposed. The topology is used as high frequency crosstalk noise sensor in modern mobile communication SoC applications. The design is based on a differential amplifier input stage combined with CMOS inverters as analog amplifiers in a Cherry-Hooper topology. The sensor performance is demonstrated via simulation results in an RFCMOS 65 nm process with a gain of 5.7 dB in a frequency range from 24 MHz up to 15 GHz, and –1 dB compression point of 107 mV, appearing as the most advanced and high performance noise sensor in the literature.

Including Substrate Losses and Noise in a Quantum Mechanical Model of a Josephson Traveling-Wave Parametric Amplifier

Substrate losses affect the performance of dispersive readout of superconducting qubits. We present a quantum mechanical model of a Josephson traveling-wave parametric amplifier, including substrate losses and the associated noise contributions. Losses and noise are introduced by coupling the system Hamiltonian to a bosonic bath, where the coupling constants can be related to the loss tangent of the transmission line substrate. Closed-form solutions for the temporal evolution of discrete mode operators in the presence of losses and noise are derived, under the assumption of a strong classical pump mode. A careful analysis of the loss-induced noise contributions can lead to the formulation of limits for the scaling of ultra-low noise qubit readout.

Plesiochronous Spread Spectrum Clocking With Guaranteed QoS for In-Band Switching Noise Reduction

Spread spectrum clocking (SSC) conventionally uses frequency modulation (FM) to suppress digital switching noise in the frequency domain. While clock-FM effectively reduces spectral noise peaks, it maintains the synchronous operation per cycle with total noise unchanged. In this paper, we introduce plesiochronous design as a general applicable de-synchronization solution for the spectral switching noise optimization with guaranteed quality-of-service. By modeling on-chip aperiodic supply current as a poly-cyclostationary random process, we theoretically prove that digital plesiochronous design contributes to reducing both, total and peak switching noise, in a harmonic frequency band of interest logarithmically proportional to the number of adopted clock domains over the synchronous baseline. A complete framework is also developed to implement plesiochronous design with the optimal clock domain partitioning and FIFO-based synchronization that features a minimum depth of six by employing Johnson encoding fully compatible with mainstream design flow. Validated on a 130nm pipelined FFT test chip across 25 dies thus taking process variations into account, our plesiochronous SSC achieves on average 5.1dB total power reductions in addition to 12.8dB peak power reductions of substrate noise at the clock fundamental frequency, which match our predictions, with only marginal hardware overhead in terms of cell area and power consumption.

Power Pad Based on Structure Stacking for Ultralow-Power Three-Axis Capacitive Sensing Applications

Ultralow-power sensing systems are a trend in handheld devices. The leakage-current-induced power consumption of traditional power pads has not been able to satisfy the specifications of three-axis ultralow-power sensing systems at high temperatures. In this paper, we present a transient detector and delay cell based on resistor and capacitor charge and discharge, two layers of structure stacking based on a metal–oxide–semiconductor, and gate-driven/substrate-driven/gate and substrate-driven methods to guide away the electrostatic current when electrostatic discharge events occur without influencing the three-axis ultralow-power sensing system. Then, we propose a stacking structure based on a metal–oxide–semiconductor to decrease leakage-current-induced power consumption, which is proportional to temperature. Moreover, we analyze whether the gate-driven/substrate-driven/gate method or substrate-driven method is most cost effective as well as the mechanism of substrate noise suppression of the two layers of structure stacking. The power pad based on the gate-driven metal–oxide–semiconductor with three structural stacks, power pad based on the gate-driven metal–oxide–semiconductor with structural stacking, power pad based on the substrate-driven metal–oxide–semiconductor with structural stacking, and the power pad based on both the gate-driven and substrate-driven metal–oxide–semiconductors with structural stacking have an electrostatic discharge standard with both positive and negative modes higher than 8/8, 8/8, 5/- kV, and 5.5/- kV for the human body model and an electrostatic discharge standard with both positive and negative modes higher than 1000/1000, 600/550, 500/- V, 300/- V for the machine model. The leakage-current-induced power consumption of the power pad based on the gate-driven metal–oxide–semiconductor with structure stacking, the power pad based on the substrate-driven metal–oxide–semiconductor with structure stacking, the power pad based on both the gate-driven, and the substrate-driven metal–oxide–semiconductor with structure stacking are approximately 3.5 pW/16.45 nW, 20 pW/- nW, and 2.89 pW/16.89 nW at 25/125 °C when the voltage of the input pin was 1.0 V.

A Scalable Discrete-Time Integrated CMOS Readout Array for Nanopore Based DNA Sequencing

This paper introduces a high-speed mixed-signal readout array in 130-nm CMOS for the amplification and digitization of picoampere-range signals. Its design is inspired by the needs of emerging DNA sequencing technologies based on biological nanopore sensors. To overcome switching and substrate noise this system adopts an in-pixel analog-to-digital converter (ADC) architecture and a novel readout technique while consuming 10x less power than similar designs described in the literature. The in-pixel ADC architecture is inherently scalable and immune to electrical interference which can be extended to 100s of channels. With a 5 pF input capacitance, the amplifiers achieve a maximum bandwidth of 100 kHz and demonstrate a noise floor as low as 4 fA/ $\sqrt {\text{Hz}}$ and a gain in the range of $\text{G}\Omega $ at 10 kHz. Circuit noise behaviour and theoretical maximum performance estimates using behavioural models are also discussed.

When Ellipsometry Works Best: A Case Study With Transparent Conductive Oxides

As the library of potential materials with plasmonic behavior in the infrared (IR) grows, we must carefully assess their suitability for nanophotonic applications. This assessment relies on knowledge of the materials’ optical constants, best determined via spectroscopic ellipsometry (SE). Transparent conductive oxides are great candidates for IR plasmonics due to their low carrier concentration (compared to noble metals) and the ability to tailor their carrier concentration by manipulating the defect composition. When the carrier concentration becomes low enough, phonon and defect states become the dominant mechanisms of absorption in the IR spectral range, leading to near-IR (NIR) tailing effects. These NIR tailing effects can be misinterpreted for free carrier absorption, rendering NIR-visible-ultraviolet-SE (NIR-VIS-UV-SE) incapable of reliably extracting the carrier transport properties. In this work, we report the limitations of NIR-VIS-UV and IR-SE (in terms of carrier concentration) by investigating the transport mechanisms of indium tin oxide, aluminum-doped zinc oxide and gallium-doped zinc oxide. We find regions of carrier concentration where NIR-VIS-UV-SE cannot reliably determine the transport properties and we designate material-dependent and application-specific confidence factors for this case. For IR-SE, the story is more complex, and so we investigate the multifaceted influences on the limitations, such as phonon behavior, grain size, presence of a substrate, film thickness, and measurement noise. Finally, we demonstrate the importance of identifying the IR optical constants directly via IR-SE (rather than by extrapolation from NIR-VIS-UV-SE) by means of comparing specific figures of merits (Faraday and Joule numbers), deemed useful indicators for plasmonic performance.

Sign-ambiguity-free retrieval of electromagnetic properties of bianisotropic metamaterials

We propose a retrieval procedure for extraction of electromagnetic properties of bianisotropic metamaterial (MM) slabs involving no sign-ambiguity. Toward this end, as different from the studies in the literature, we derive a closed-form expression for the intermediate variable T (propagation factor) and use it to obtain sign-ambiguity-free electromagnetic properties of bianisotropic MM slabs. We utilized 3D CST Microwave Studio to simulate scattering parameters of a bianisotropic MM slab composed of circular split-ring-resonators and to validate the derived closed-form expressions. The effects of substrate loss, geometrical parameters, and noise in S-parameters were examined to assess the capability of the proposed method.

An extensive survey on reduction of noise coupling in TSV based 3D IC integration

3D Integration technology is probably the best methodologies among others which suits CMOS applications with in various layers of devices are stacked with high thickness interconnects between the layers. In 3D IC structure electrical and thermal models are introduced for the interface between Through-Silicon-Via’s (TSV’s). TSV’s can be used to enable the 3-D platform; however this TSV’s will represent additional concerns. TSV-to-substrate and TSV-to-TSV noise coupling is assessed inside the 3-D IC’s. A vertical TSV’s design is proposed to reduce the area per TSV, capacitive coupling and effective inductance as compared with the other classical design patterns. TSV’s and substrate noise coupling is one of the major drawbacks in 3D IC. Some of the researchers have tried to overcome the problems in TSV based 3D IC due to noise coupling using different models, materials and different circuit techniques. This paper shows the complete road map for the noise coupling reduction in future IC integration.