Substrate Noise Generation Research Articles

Emulation of high-frequency substrate noise generation in CMOS digital circuits

A noise emulator is based on the capacitor charging modeling and generates power and substrate noises expected in a CMOS digital integrated circuit. An off-chip near-magnetic-field sensor indirectly characterizes the distribution of clock timing and the adjustability of skews within on-chip digital circuits. An on-chip noise monitor captures power and substrate noise waveforms and evaluates noise frequency components in a wide frequency bandwidth. A 65 nm CMOS prototype demonstrated power and substrate noise generation in a variety of operating scenarios of digital integrated circuits. Power noise generation emulated at 125 MHz exhibits the enhancements of high-order harmonic components after deskewing at a timing resolution of 37.8 ps, as is specifically seen in more than 10 dB enlargement of the substrate noise component at 2.1 GHz.

Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate

Substrate noise generated by the digital circuits on a mixed-signal IC can severely disturb the analog and RF circuits sharing the same substrate. Simulations at the circuit level of the substrate noise coupling in large systems-on-chip (SoCs) do not provide the necessary understanding in the problem. Analysis at a higher level of abstraction gives much more insight in the coupling mechanisms. This paper presents a physical model to estimate and understand the substrate noise generation by a digital modem, the propagation of this noise and the resulting performance degradation of LC tank VCOs. The proposed linearized model is fast to derive and to evaluate, while remaining accurate. It is validated with measurements on two test structures: a reference design and a design with a p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /n-well (digital) guard ring. Both structures contain a functional 40k gate digital modem and a 0.18 mum 3.5 GHz CMOS LC-VCO on a lightly-doped substrate. In both cases, the model accurately predicts the level of the spurious components appearing at the VCO output due to the digital switching activity. The error remains smaller than 3 dB. Finally, we demonstrate how the proposed model enables a systematic and controlled isolation strategy to suppress substrate noise coupling problems. As an example, the model is used to determine suitable dimensions for a digital guard ring

Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding

In a synchronous clock distribution network with negligible skews, digital circuits switch simultaneously on the clock edge; therefore, they generate a lot of substrate noise due to the resulting sharp peaks on the supply current. A solution is to split a large design in different clock regions and introduce intentional clock skews between them, while taking the timing constraints into account. In this paper, the authors present a complete design flow to optimize the clock tree for less substrate-noise generation in large digital systems. It proposes a technique to assign combinatorial cells and flip-flops to the clock regions. It also takes into account the impact of unintentional clock skew such as jitter on the computed skews in order to assure a robust design. During the optimization, it uses compressed supply-current profiles to improve the CPU time. Experimental results show more than a factor-of-2 reduction in substrate-noise generation from large digital circuits of which the skews are optimized

Evolution of substrate noise generation mechanisms with CMOS technology scaling

Substrate noise is a major obstacle for single-chip integration of mixed-signal systems. To reduce this problem and to assess its evolution with CMOS technology scaling, the different mechanisms that generate substrate noise and their dependencies on different parameters need to be well understood. In this paper, we show that with downscaling of the technology, substrate noise due to supply coupling becomes the dominant coupling mechanism when the chip substrate is directly biased with the digital ground. With Kelvin ground substrate biasing on the other hand, source/drain capacitive coupling becomes the dominant coupling mechanism. Further, we show that with downscaling, the peak value of the supply coupling noise component becomes more dependent on the relative ratio of the switching capacitance to the nonswitching capacitance, which is formed by the circuit decoupling and the nonswitching circuit elements, rather than the Ldi/dt noise. These insights illustrated in a quantitative framework are believed to be very useful for the systematic use of digital low-noise design techniques in future CMOS technologies.

SWAN: high-level simulation methodology for digital substrate noise generation

Substrate noise generated by the switching digital circuits degrades the performance of analog circuits embedded on the same substrate. It is therefore important to know the amount of noise at a certain point on the substrate. Existing transistor-level simulation approaches based on a substrate model extracted from layout information are not feasible for digital circuits of practical size. This paper presents a complete high-level methodology, which simulates a large digital standard cell-based design using a network of substrate macromodels, with one macromodel for each standard cell. Such macromodels can be constructed for both EPI-type and bulk-type substrates. Comparison of our substrate waveform analysis (SWAN) to several measurements and to several full SPICE simulations indicates that the substrate noise is simulated with our methodology within 10%-20% error in the time domain and within 2 dB relative error at the major resonance in the frequency domain. However, it is several orders of magnitude faster in CPU time than a full SPICE simulation.

Simulation of substrate coupling in mixed-signal IC's using an efficient and real-time macromodel

Substrate noise is a key problem in the design of large mixed-signal circuits. Estimating the interaction from large digital blocks and its effect on on-chip performance degradation is extremely important in mixed-signal IC design and is a major challenge in system-on-chip(SOC) design. In this paper, we address efficient methods and models to simulate substrate noise coupling at high level design with the real-time capability .Techniques to directly or indirectly compute the values of the elements in the cell macromodel are described. This approach makes it possible to predict substrate noise generation of large digital blocks in a very efficient and fast way and makes it compatible with the design flow of mixed-signal circuits. For verification, the macromodel accuracy is demonstrated in some example circuits.

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate

Substrate noise is a major obstacle for mixed-signal integration. Ground bounce is a major contributor to substrate noise generation due to the resonance caused by the inductance and the Vdd-Vss admittance that consists of the on-chip digital circuit capacitance of the MOS transistors, the decoupling, and the parasitics arising from the interconnect. In this paper, we address: 1) the dependence of the Vdd-Vss admittance on the different states of the circuit, the supply voltage, and the interconnect, and 2) the computation of the total supply current with ground bounce. By using a fast and accurate macromodeling approach, the Vdd-Vss admittances of several test circuits are computed with 2%-3% error relative to the values simulated from the complete SPICE level netlist, but several orders of magnitude faster in CPU time and with 10% maximum error relative to the measurements on a test ASIC fabricated in a 0.18-/spl mu/m CMOS process on a high-ohmic substrate with 18 /spl Omega//spl middot/cm resistivity. The measurements also show that this admittance mainly depends only on the connectivity of the gates to the supply rail rather than their connectivity among each other.

Modeling and experimental verification of substrate noise generation in a 220-kgates wlan system-on-chip with multiple supplies

Substrate noise is a major obstacle for mixed-signal integration. While the power consumption scales linearly with the clock frequency, substrate noise does not have this scaling due to the resonances in the transfer function of the supply current to the substrate. This paper addresses a practical technique to estimate the substrate noise frequency spectrum of a large mixed-mode System-on-Chip (SoC) with multiple supplies and embedded memories. The results have been verified with substrate noise measurements on a 60-MHz 220-Kgates telecom SoC implemented in a 0.35 /spl mu/m CMOS process on an EPI-type substrate. We compute a linear chip-level substrate model together with the single-cycle representation of piecewise-linear noise sources of three supply regions used in this ASIC. Based on this model we accurately estimate the four major resonances in the substrate noise spectrum and their relative magnitudes with 2 dB relative error at the major resonance with respect to measurements. We also present substrate noise measurements at different operating modes of the WLAN receiver. These measurements show that output I/O buffers generate significant substrate noise where an increase of 44% is measured for substrate noise peak-to-peak value due to the additional simultaneous switching of six output I/O buffers with already fully switching datapath and two output I/Os.

Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification

More and more system-on-chip designs require the integration of analog circuits on large digital chips and will therefore suffer from substrate noise coupling. To investigate the impact of substrate noise on analog circuits, information is needed about digital substrate noise generation. In this paper, a recently proposed simulation methodology to estimate the time-domain waveform of the substrate noise is applied to an 86-Kgate CMOS ASIC on a low-ohmic epi-type substrate. These simulation results have been compared with substrate noise measurements on this ASIC and the difference between the simulated and measured substrate noise rms voltage is less than 10%. The simulated time domain waveform and frequency spectrum of the substrate noise correspond well with the measurements, indicating the validity of this simulation methodology. Both measurements and simulations have been used to analyze the substrate noise generation in more detail. It has been found that direct noise coupling from the on-chip power supply to the substrate dominates the substrate noise generation and that more than 80% of the substrate noise is generated by simultaneous switching of the core cells. By varying the parameters of the simulation model, it has been concluded that a flip-chip packaging technique can reduce the substrate noise rms voltage by two orders of magnitude when compared to traditional wirebonding.

Analysis and experimental verification of digital substrate noise generation for epi-type substrates

Substrate coupling in mixed-signal IC's can cause important performance degradation of the analog circuits. Accurate simulation is therefore needed to investigate the generation, propagation, and impact of substrate noise. Recent studies were limited to the time-domain behavior of generated substrate noise and to noise injection from a single noise source. This paper focuses on substrate noise generation by digital circuits and on the spectral content of this noise. To simulate the noise generation, a SPICE substrate model for heavily doped epi-type substrates has been used. The accuracy of this model has been verified with measurements of substrate noise, using a wide-band, continuous-time substrate noise sensor, which allows accurate measurement of the spectral content of substrate noise. The substrate noise generation of digital circuits is analyzed, both in the time and frequency domain, and the influence of the different substrate noise coupling mechanisms is demonstrated. It is shown that substrate noise voltages up to 20 mV are generated and that, in the frequency band up to 1 GHz, noise peaks are generated at multiples of the clock and repetition frequency. These noise signals will strongly deteriorate the behavior of small signal analog amplifiers, as used in integrated front-ends.