Effect Of Substrate Noise Research Articles

Impact of single event transient effect on adiabatic logic circuits

The evolution of the modern Complementary Metal Oxide Semiconductor technology has led to the scaling of the transistor size to nanometers. This has resulted in significant benefits to integrated circuits, such as higher speed, smaller circuit size and lower operating voltage. However, this smaller size and lower operating voltage have become highly susceptible to operational disturbances such as signal coupling, substrate noise, and single event effects caused by ionizing particles. Single Event Transient occurs when a high-energy particle strikes a combinational logic circuit. The charge deposited by the particle causes a transient voltage disturbance to load incorrect data. In this work, the impact of Single Event Transient on total power dissipation and the delay of static complementary logic is analyzed. Different circuits like basic inverter, adiabatic inverter, chain of inverters of complementary and adiabatic logic have been selected for the analysis. The technology node used for this analysis is 180 nm and 90 nm using Cadence Virtuoso. The result shows that on scaling, the effect of Single Event Transient is increased, and the use of an adiabatic logic reduces the power by 15% compared to conventional static logic circuits.

Sign-ambiguity-free retrieval of electromagnetic properties of bianisotropic metamaterials

We propose a retrieval procedure for extraction of electromagnetic properties of bianisotropic metamaterial (MM) slabs involving no sign-ambiguity. Toward this end, as different from the studies in the literature, we derive a closed-form expression for the intermediate variable T (propagation factor) and use it to obtain sign-ambiguity-free electromagnetic properties of bianisotropic MM slabs. We utilized 3D CST Microwave Studio to simulate scattering parameters of a bianisotropic MM slab composed of circular split-ring-resonators and to validate the derived closed-form expressions. The effects of substrate loss, geometrical parameters, and noise in S-parameters were examined to assess the capability of the proposed method.

Simulation Methodology and Evaluation of Through Silicon Via (TSV)-FinFET Noise Coupling in 3-D Integrated Circuits

Bulk FinFETs have emerged as the solution to short-channel effects at the 22-nm technology node and beyond. The capability of 3-D stacking of dies from various technologies will eventually enable stacking FinFET dies within 3-D integrated circuits. Within 3-D circuits, through silicon vias (TSVs) are a known source of substrate noise in planar bulk technologies. While FinFETs are expected to demonstrate superior noise immunity relative to planar devices due to superior gate control over and volume inversion of the active fin, the impact of TSV noise on FinFETs has not been previously quantified. To evaluate TSV-FinFET noise coupling, we develop in this paper a simulation methodology that extends the state of the art by accurately modeling substrate noise due to digital signals on nearby TSVs and improving the extraction of substrate circuit models from full-wave electromagnetic simulations. To overcome the lack of high-fidelity FinFET SPICE models that accurately capture the effects of substrate noise, we use high-fidelity technology computer-aided design (TCAD) FinFET models. Our results show that FinFETs exhibit an order of magnitude less leakage current noise transients, and two orders of magnitude less saturation current noise transients, relative to comparable planar technologies. Our findings are generalizable, showing that FinFETs are significantly more robust to substrate noise than equivalent planar devices.

Experimental Study on Substrate Noise Effects of a Pulsed Clocking Scheme on PLL Performance

In this brief, the substrate noise effects of a pulsed clocking scheme on the output spur level, the phase noise, and the peak-to-peak (Pk-Pk) deterministic period jitter of an integer-N charge-pump phase-locked loop (PLL) are demonstrated experimentally. The phenomenon of noise coupling to the PLL is also explained through experiments. The PLL output frequency is 500 MHz and it is implemented in the 0.13- μm CMOS technology. Measurements show a reduction of 12.53 dB in the PLL output spur level at an offset of 5 MHz and a reduction of 107 ps in the Pk-Pk deterministic period jitter upon reducing the duty cycle of the signal injected into the substrate from 50% to 20%. The results of the analyses suggest that using a pulsed clocking scheme for digital systems in mixed-signal integration along with other isolation techniques helps reduce the substrate noise effects on sensitive analog/radio-frequency circuits.

Design of a 2.5-GHZ QVCO robust against high frequency substrate noise

4. CONCLUSIONS A new compact handheld antenna utilizing a microstrip fed monopole like arm capacitively coupled with a small patch is designed, prototyped, and measured for tri-band applications. The prototyped antenna shows wide bandwidths (10 dBreturn loss) of 170 MHz (0.885 to 1.055 GHz), 0.9 GHz (2.3-3.2 GHz), and 1.61 GHz (5.51-7.12 GHz) in the three operating bands respectively with stable radiation characteristics. ABSTRACT: This work presents the design procedure followed to obtain a low-power voltage-controlled oscillator (VCO) robust against high-frequency substrate noise, using as a demonstrator a 2.5 GHz VCO with quadrature outputs (QVCO) based on a 5-GHz LC tank resonant VCO (LC-VCO) and frequency divider. A simple, intuitive, and easy to handle analytical model is proposed to identify the design parameters that contribute to the performance degradation of LC-VCOs due to the effect of high frequency substrate noise. The guidelines obtained have been applied in the design of the low-power QVCO. Finally, the work discusses several trade-offs that can be used to maximize the immunity of a LC-VCO against substrate noise. V C 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:1632-1637, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26043

Multi-Path Analog Circuits Robust to Digital Substrate Noise

A multi-path structure is proposed for reduction in effect of digital substrate noise which degrades analog circuit performance. As an example low-pass filters are implemented in a 0.18-μm CMOS process. 11-dBm reduction in digital substrate noise is achieved as compared with a conventional structure.

Study of substrate noise and techniques for minimization

The effects of substrate noise on analog circuits in a mixed-signal chip are described and analyzed based on measured results. Experimental data from a 0.25-/spl mu/m CMOS test chip reveals that substrate noise generated by digital circuits couples into analog circuits through circuit asymmetries and device nonlinearity, degrading analog circuit performance. In particular, a delta-sigma modulator shows over 20-dB reduction of signal-to-noise-plus-distortion ratio (SNDR) in the presence of large toggling digital inverters. To combat the effects of substrate noise, the technique of active substrate noise shaping is investigated. An implementation of active substrate noise shaping on the same test chip demonstrates over 10-dB improvement in SNDR in the 0-20-kHz band of the delta-sigma modulator in the presence of toggling digital inverters emulating I/O drivers. This technique complements existing substrate noise reduction techniques for integrated circuits without a significant penalty in power and does not require modification of analog nor digital circuits.

A Fast Macro-Model for Substrate Coupling and Ground Bounce Induced Substrate Noise Simulation in Mixed Signal VLSI

This paper discusses a novel substrate modeling technique for the simulation of substrate noise in mixed signal VLSI systems. This model yields to easy merger with the SPICE simulation netlist for the complete pre and post layout estimation of substrate noise effects in large mixed signal VLSI chips. Compared to previous numerous efforts in substrate noise modeling ranging from finite element methods (FEM) to boundary elements methods (BEM), this model, based on a finite sheet resistor slicing scheme also incorporates the effect of supply rail bounce due to bonding wire inductances, and, provides realistic estimates of substrate noise effects with a high degree of computational efficiency. Substrate noise simulations were done using a 0.18 μm TSMC CMOS process technology using typical process parameters. A differential switched capacitor sample and hold circuit and a linear differential transconductor stage was used for the performance evaluation of this novel substrate model. Simulation results indicate a typical increase in Total Harmonic Distortion (THD) by atleast 6 dB due to the substrate noise effects, which corresponds to a performance loss by around 1-b precision. Also, the substrate noise effects are found to be proportional to the oversampling ratio (i.e., the digital clocking rate with respect to the input signal) and the net number of logic transitions at each register transfer instance in the mixed signal chip.

Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver

The influence of substrate noise coupling on the performance of a low-noise amplifier (LNA) for a CMOS GPS receiver has been investigated both analytically and experimentally. A frequency-domain approach has been used to model both noise injection into the substrate from digital circuitry integrated on the same chip and the mechanisms by which that noise can affect analog circuit behavior. The results of this study reveal that substrate noise can modulate the LNA input signal as well as couple directly to the amplifier's output.

Floquet theory and non-linear perturbation analysis for oscillators with differential-algebraic equations

Oscillators are key components of electronic systems. In RF communication systems, they are used for frequency translation of information signals and for channel selection, and in digital electronic systems, they are used as a time reference, i.e. a clock signal, in order to synchronize operations. Undesired perturbations in practical electronic systems adversely affect the spectral and timing properties of oscillators, which is a key performance limiting factor, being a major contributor to bit-error-rate (BER) of RF communication systems, and creating synchronization problems in clocked and sampled-data systems. Characterizing how perturbations affect oscillators is therefore crucial for practical applications. The traditional approach to analysing perturbed nonlinear systems (i.e. linearization) is not valid for oscillators. In this paper, we present a theory and efficient numerical methods, for non-linear perturbation and noise analysis of oscillators described by a system of differential-algebraic equations (DAEs). Our techniques can be used in characterizing phase noise and timing jitter due to intrinsic noise in IC devices, and evaluating the effect of substrate and supply noise on the timing properties of practical oscillators. In this paper, we also establish novel results for periodically time-varying systems of linear DAEs, which we rely on in developing the above theory and the numerical methods. Copyright © 2000 John Wiley & Sons, Ltd.

A dynamic clock synchronization technique for large systems

This paper reports on a circuit technique which can be used to reduce the clock skew in ULSI and WSI systems. It is suitable for large systems which are divided into isochronic modules with locally optimized clock distribution. The inter-module clock distribution uses tunable delay elements to compensate for the differences in the phase delay of the individual modules. The delay elements introduce a phase shift to the clock signals going to each region to align the clock edges at the leaves of the local clock trees. This technique is dynamic in the sense that it guarantees clock synchronization in the presence of process or ambient variations. Whenever the clock skew exceeds a specific limit, the clock synchronization systems is activated to restrain the skew. The advantage of this technique over using phase locked loop circuits is that it saves power consumption and area. In addition, its lock-in time is much shorter. Experiments have shown that using the tunable delay element approach is capable of reducing the skew to less than 100 ps. A stability criterion was developed. The effect of substrate and power supply noise on the synchronization scheme was also investigated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

New CMOS floating voltage-controlled resistor

A new CMOS floating voltage-controlled resistor for continuous-time filtering applications is described. The value of the resistance simulated by this circuit is independent of the threshold voltage of the transistors. This allows us to obtain a larger input range and also minimises the effects of threshold voltage mismatches and substrate noise. These improvements are obtained at the expense of a higher sensitivity to mismatches in the W/L ratios of the transistors.