Substrate Leakage Research Articles

Leakage and Thermal Reliability Optimization of Stacked Nanosheet Field-Effect Transistors with SiC Layers.

In this work, we propose a SiC-NSFET structure that uses a PTS scheme only under the gate, with SiC layers under the source and drain, to improve the leakage current and thermal reliability. Punch-through stopper (PTS) doping is widely used to suppress the leakage current, but aggressively high PTS doping will cause additional band-to-band (BTBT) current. Therefore, the bottom oxide isolation nanosheet field-effect transistor (BOX-NSFET) can further reduce the leakage current and become an alternative to conventional structures with PTS. However, thermal reliability issues, like bias temperature instability (BTI), hot carrier injection (HCI), and time-dependent dielectric breakdown (TDDB), induced by the self-heating effect (SHE) of BOX-NSFET, become more profound due to the lower thermal conductivity of SiO2 than silicon. Moreover, the bottom oxide will reduce the stress along the channel due to the challenges associated with growing high-quality SiGe material on SiO2. Therefore, this method faces difficulties in enhancing the mobility of p-type devices. The comprehensive TCAD simulation results show that SiC-NSFET significantly suppresses the substrate leakage current compared to the conventional structure with PTS. In addition, compared to the BOX-NSFET, the stress reduction caused by the bottom oxide is avoided, and the SHE is mitigated. This work provides significant design guidelines for leakage and thermal reliability optimization of next-generation advanced nodes.

Manufacturing and characterization of CMOS-MEMS magnetic field microsensors with isolated cavities

The study investigates a magnetic field (MF) microsensor with isolated cavities manufactured utilizing complementary metal oxide semiconductor (CMOS)-microelectromechanical system technology. This microsensor, which is a type of magnetic transistor, comprises four identical magnetic sensing elements, each featuring an emitter, a base, two collectors, and an additional collector. The magnetic transistor operates on the principles of the Lorentz force. This force is employed to modulate the electrical properties of the transistor, responding to changes in the surrounding MF. The MF microsensor chip is fabricated using the commercial CMOS process. Upon completing the CMOS process, post-processing is employed to etch the silicon substrate of the microsensor chip, generating isolated cavities on the silicon substrate. These isolated cavities effectively mitigate substrate leakage current, enhancing the sensitivity of the MF microsensor. The experimental results reveal that the sensitivity of the microsensor without isolated cavities is 60 mV T−1. In contrast, the microsensor with isolated cavities exhibits a sensitivity of 121 mV T−1. A comparison between microsensors with and without isolated cavities depicts that the sensitivity of the MF microsensor with isolated cavities doubled.

Novel partial punch-through-stopper scheme for substrate leakage optimization of nanosheet field-effect transistors

A novel and practicable partial punch-through-stopper (p-PTS) scheme beneath the gate area is proposed for the substrate leakage current suppression in the gate-all-around (GAA) nanosheet field-effect transistors (NSFETs). Thanks to the weakened electric field and widened tunneling length caused by the lightly doped substrate under the drain region, this p-PTS scheme can not only achieve a low PT current comparable to the conventional full-PTS (f-PTS) scheme, but also substantially reduce the BTBT current of drain–substrate junction by about two orders of magnitude. Moreover, the key parameters of the p-PTS scheme, such as p-PTS doping concentration (Np-PTS), thickness (Tp-PTS) and width (Wp-PTS), are systematically optimized and analyzed. As a result, compared to the conventional f-PTS scheme, p-PTS scheme exhibits a larger process window and better immunity of leakage current to process variations. The above results indicate that the proposed p-PTS scheme is one of the most promising methods for suppressing substrate leakage current in NSFET.

Impedance characterization of substrate leakage in wafer bonded CMUTs

This work investigates substrate leakage in Capacitive Micromachined Ultrasonic Transducers, (CMUTs) having thin backings. CMUTs produced with solid or rigid substrates have a high Q resonance with flat baseline. However, if the operating wavelength of CMUT becomes larger than the thickness of substrate the real part of cell impedance shows elevated baselines with more leakage at DC than at higher frequencies. When a clamped CMUT membrane is excited harmonically the vibrations produced are counterbalanced by the backing medium. Hence some of the energy is coupled to substrate as loss resulting in a lower mechanical Q of resonance. We first derive this energy coupled to the backing medium using FEA analysis considering the velocity field and associated tensile stresses in a thin backing. Substrate impedance is found numerically from isotropic damping of dispersive elastic waves in the backing. This backing impedance is introduced as a shunt mechanical loss across the transduction force in equivalent circuit model. We characterize the measured impedance of CMUT cells with both FEMs and linear circuit models. Simulations results closely agree with the measured impedance levels, frequency and bandwidth of resonance.

Novel process integration flow of germanium-on-silicon FinFETs for low-power technologies

Germanium channel FinFET transistors process integration on a silicon substrate is a promising candidate to extend the complementary metal–oxide–semiconductor semiconductor roadmap. This process has utilized the legacy of state-of-art silicon fabrication process technology and can be an immediate solution to integrate beyond Si channel materials over standard Si wafers. The fabrication of such devices involves several complicated technological steps, such as strain-free epi layers over the Si substrate to limit the substrate leakage and patterning of narrow and sharp fins over germanium (Ge). To overcome these issues, the active p-type germanium layers were grown over n-type germanium and virtual substrates. The poly ((4-(methacryloyloxy) phenyl) dimethyl sulfoniumtriflate) was utilized as a polymeric negative tone e-beam resist for sub-20 nm critical dimensions with low line edge roughness, line width roughness, and high etch resistance to pattern p-Ge fins to meet these concerns. Here, the devices use the mesa architecture that will allow low bandgap materials only at the active regions and raised fins to reduce the active area interaction with the substrate to suppress leakage currents. This paper discusses the simple five-layer process flow to fabricate FinFET devices with critical optimizations like resist prerequisite optimization conditions before exposure, alignment of various layers by electron beam alignment, pattern transfer optimizations using reactive ion etching, and bilayer resist for desired lift-off. The Ge-on-Si FinFET devices are fabricated with a width and gate length of 15/90 nm, respectively. The devices exhibit the improved ION/IOFF in order of ∼105, transconductance Gm ∼86 μS/μm, and subthreshold slope close to ∼90 mV/dec.

Design and Analysis of a Wideband K/Ka-Band CMOS LNA Using Coupled-TL Feedback

We demonstrate a low power (PD) 22-33 GHz CMOS low-noise amplifier (LNA) with low noise-figure (NF) and small group-delay (GD) variation for 28 GHz 5G system. Body-selfforward-bias (BSFB) technique, i.e., connection of transistor’s body to drain via body resistance, is used for threshold and supply voltage reduction, and substrate leakage suppression. Gain and NF enhancement at the same PD is achieved because lower VDD and higher transconductance (due to larger bias current) are used. Current-reused topology is used for low PD. Coupled transmission -line (TL) feedback neutralization technique is proposed for further gain and NF enhancement. The feedback from output (drain) to input (gate) via gate-drain capacitance (Cgd) can be cancelled by the feedback from drain (through source) to gate via the coupled TL and gate-source capacitance (Cgs). The LNA consumes 12.2 mW and achieves S21 of 16 dB, 3 dB bandwidth (f3dB) of 11 GHz (22-33 GHz), minimum NF (NFmin) of 2.5 dB, average NF (NFavg) of 3.1 dB, and GD variation of ±6 ps for 22-33 GHz, and figure-of-merit (FOM) of 91.7 GHz. Moreover, the LNA achieves input third-order intercept point (IIP3) of -3 dBm. The NF and FOM are one of the best results ever reported for LNAs with f3dB greater than 7 GHz and PD lower than 15 mW.

InAlN cladding implementation in green superluminescent diodes and lasers

We demonstrate state-of-the-art superluminescent light emitting diodes emitting in the green spectral range with InAlN n-type claddings. The implementation of an InAlN optical blocking layer for suppressing modal substrate leakage leading to high farfield quality is first reported. An optimized structure by optical mode simulations featuring a bottom n-type InAlN cladding layer is then presented. Compared to conventional AlGaN cladding based devices, the electro-optical performance, optical confinement, and modal substrate leakage are greatly improved. Performance improvements in green laser diode devices are also presented.

A 12.4–32 GHz CMOS Down-Conversion Mixer for 28 GHz 5G New Radio (NR)

We report a low voltage (VDD) and power (PDC) 12.4–32 GHz CMOS down-conversion mixer with high conversion gain (CG) for 28 GHz 5G communications. A quarter-wavelength (λ/4) transmission line (TL) and a coupling capacitor (Cc), named the λ/4-TL-C-based coupler, is proposed. This is the way to attain low-VDD, independent RF transconductance (gm)-stage bias, harmonic suppression, and near perfect coupling from the RF gm stage to the LO switch transistors. The body-self-forward-bias (BSFB) technique, i.e., connection of the gm-stage transistors’ body to drain via a large body resistance, is used for threshold voltage (Vth) and VDD reduction and substrate leakage suppression. CG and noise figure (NF) enhancement at the same or even a lower PDC is achieved because lower VDD and higher gm (due to larger bias current) are used. To facilitate the RF measurement, a compact Wilkinson-power-divider-based balun with small-phase deviation and amplitude imbalance is included at RF and LO inputs. The mixer consumes 6.5 mW and achieves a CG of 14.4 ± 1.5 dB for 12.4–32 GHz (i.e., 3 dB bandwidth (f3dB) of 19.6 GHz), a lowest noise figure (NFmin) of 7 dB, and figure-of-merit (FOM) of 0.023, which is one of the best results ever reported for millimeter-wave (mm-wave) down-conversion mixers with an f3dB larger than 10 GHz and PDC lower than 10 mW.

Optimization of bulk sensitivity for strip, slot, and subwavelength grating-based waveguides for dual-polarization operation.

We propose a dual-polarization optimization method for the bulk sensitivity of silicon-on-insulator (SOI) waveguides by defining a multi-objective function that accounts for the substrate leakage losses. The proposed optimization method was used to design micro-ring resonator bulk sensors with strip, slot, subwavelength grating, and subwavelength grating slot waveguides. The subwavelength grating slot waveguide has a bulk sensitivity of 520 nm/RIU and 325 nm/RIU for the TE and TM modes, respectively, both of which are higher than the bulk sensitivities of strip, slot, and subwavelength grating waveguides. Moreover, our Monte Carlo analysis shows that the subwavelength grating slot waveguide has the highest immunity to fabrication errors.

A Bootstrap Diode Emulator Integration to 600 V N-Type Epitaxial Platform for High Voltage Gate Driver IC

An integrated bootstrap diode emulator is experimentally investigated, including a high voltage (HV) junction field effect transistor (JFET) with adjustable pinch-off voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{{\mathrm {P}}}$ </tex-math></inline-formula> ) and a medium voltage (MV) diode. It features substrate leakage current suppression, and it can be integrated to 600 V N-type epitaxial (N-epi) Bipolar-CMOS-DMOS (BCD) technology. The HV JFET is formed in a part of the high voltage isolation region and the MV diode is formed outside of the high voltage isolation region. In HV JFET, the extending P-type buried layer (PBL) is introduced as the back gate to adjust <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{{\mathrm {P}}}$ </tex-math></inline-formula> of JFET. Since JFET is easy to pinch-off, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{{\mathrm {P}}}$ </tex-math></inline-formula> of JFET is much lower than breakdown voltage (BV) of MV diode, the bootstrap diode emulator can obtain a high BV of 970 V at block mode. Moreover, BV of MV diode depends on the thickness and doping concentration of N-epi rather than the doping concentration of N-type buried layer (NBL). Thus, the highly doped NBL layer can be introduced in the junction of N-epi/P-sub to further suppress the substrate leakage current at conduction mode. Besides, due to the fact that HV JFET is a majority carrier device, the equivalent reverse recovery characteristic of the bootstrap diode emulator is also competitively, and the equivalent reverse recovery process is also qualitatively analyzed.

Leakage Optimization of the Buried Oxide Substrate of Nanosheet Field-Effect Transistors

In this work, a new buried oxide nanosheet field-effect transistor (BO-NSFET) structure is proposed for the first time as a strategy for improving the leakage of 3-nm stacked nanosheet field-effect transistors (NSFETs) by locally inserting an oxide material only under the gate region. NSFETs with punchthrough stoppers (PTSs) doping of the substrate region have been widely adopted to reduce substrate leakage; however, band-to-band tunneling (BTBT) under negative bias remains a serious problem in such devices. By only inserting the oxide material under the gate region, the electric field from the gate to the drain–substrate junction is dispersed. Furthermore, since there is no oxide material under the source and drain (S/D) region, there is no stress reduction along the channel direction coming from the silicon-on-insulator (SOI) structure. We performed technology computer-aided design (TCAD) simulations, and the results show that the proposed structure effectively reduces both the tunneling current in the NSFET with PTS structure and the OFF-current in the NSFET without PTS structure, compared with those of conventional NSFETs.

The Development of Monolithic Silicon Carbide Intracortical Neural Interfaces for Long-Term Human Implantation

Silicon Carbide (SiC) has been demonstrated as both a bio- and neuro-compatible wide-band-gap semiconductor with a high thermal conductivity and magnetic susceptibility and may be potentially compatible with human brain tissue. Two single-crystal, solid-state forms of SiC have been used to create monolithic intracortical neural implants (INI) without using physiologically exposed metals or polymers, thus eliminating many known reliability challenges in-vivo through a single, homogenous material. Amorphous SiC (a-SiC) was used to insulate 16-channel functional INI and the electrochemical and MRI compatibility (7T) performance were measured. 4H-SiC interfaces were fabricated using homoepitaxy,alternating epitaxial films of n-type and p-type forming an isolating PN junction which prevents substrate leakage current between the 16 adjacent electrodes and traces fabricated which were formed using deep-reactive ion etching (DRIE). 3C-SiC interfaces were fabricated in a similar fashion, but the epitaial conductive layers were grown on on both bulk crystalline (100) silicon and SOI wafers. In both cases a conformal coating of a-SiC was used as the top-side insulator and windows opened using RIE to allow electrochemical interaction. Electrochemical charaterization achieved through electrochemcial impedance spectroscopy (EIS) and cyclic voltammetry (CV) indicates performance on par, or exceeding, that of Pt reference electrodes with the same form fit. While magnetic resonance imaging (MRI) is an essential, non-contact method used to investigate issues with the nervous system, the high field MRI (e.g., 3 T and higher) necessary for proper diagnosis can be a safety issue for patients with INI due to inductive coupling between the powerful electromagnetic fields and the implanted device. This results in having to use lower electromagnetic field power (less than 1.5T), and therefore lower resolution, which hinders diagnostic prognosis for these patients. In this work the MRI compliance of epitaxial, monolithic SiC INI was studied. The specific absorption rate (SAR), induced heating, and image artifacts caused by the portion of the implant within a brain tissue phantom located in a 7 T small animal MRI machine were estimated and measured via finite element method (FEM) and Fourier-based simulations. Both the simulation and experimental results revealed that free-standing 3C-SiC films had no observable image artifacts compared to silicon and platinum reference materials inside the MRI at 7 T while FEM simulations predicted an ~30% SAR reduction for 3C-SiC compared to Pt. These initial simulations and experiments indicate a SiC monolithic INI may effectively reduce MRI induced heating and image artifacts in high field MRI.

A Π-shaped p-GaN HEMT for reliable enhancement mode operation

This paper presents a TCAD based investigation of virtually fabricated Π-shaped Gate p-GaN HEMT for reliable enhancement mode operation. A detailed comparison with the Conventional T-Gate counterpart, with a focus towards the trap related dispersive effect reveals the superiority of Π-shaped Gates P-GaN HEMT for suppressing both the vertical substrate and gate leakage currents, thereby enhancing the breakdown characteristics of the device. A modification of the electric fields, into a stepped profile, demonstrates effective suppression of the leakage through the surface defects, and spillover into GaN buffer, thereby mitigating the trap related dispersive effects. Dispersive effect of the two devices has also been compared using current Slump Ratio (SR) which is lower for Π-shaped Gate P-GaN HEMT. Further analysis into laterally scaled drain-access regions, demonstrates superiority of Π-shaped Gates in achieving a reliable thermal operation, and applicability of Π-shaped Gate P-GaN HEMT for future RF and High Power applications.

Optimization of Gate-All-Around Device to Achieve High Performance and Low Power with Low Substrate Leakage.

In this study on multi-nanosheet field-effect transistor (mNS-FET)—one of the gate-all-around FETs (GAAFET) in the 3 nm technology node dimension—3D TCAD (technology computer-aided design) was used to attain optimally reduced substrate leakage from options including a punch-through-stopper (PTS) doping scheme and a bottom oxide (BO) scheme for bottom isolation, with the performance improvement being shown in the circuit-level dynamic operation using the mNS-FET. The PTS doping concentration requires a high value of >5 × 1018 cm−3 to reduce gate induced drain leakage (GIDL), regardless of the presence or absence of the bottom isolation layer. When the bottom isolation is applied together with the PTS doping scheme, the capacitance reduction is larger than the on-state current reduction, as compared to when only the PTS doping concentration is applied. The effects of such transistor characteristics on the performance and capabilities of various circuit types—such as an inverter ring oscillator (RO), a full adder (FA) circuit, and a static random-access memory (SRAM)—were assessed. For the RO, applying BO along with the PTS doping allows the operating speed to be increased by 11.3% at the same power, or alternatively enables 26.4% less power consumption at the same speed. For the FA, power can be reduced by 6.45%, energy delay product (EDP) by 21.4%, and delay by 16.8% at the same standby power when BO and PTS are both applied. Finally, for the SRAM, read current (IREAD) increased by 18.7% and bit-line write margin (BWRM) increased by 12.5% at the same standby power. Through the circuit simulations, the Case 5 model (PTS doping concentration: 5.1 × 1018 cm−3, with BO) is the optimum condition for the best device and circuit performance. These observations confirm that PTS and bottom isolation applications in mNS-FETs can be utilized to enable the superior characteristics of such transistors to translate into high performance integrated circuits.

Impact of AlGaN Barrier Thickness and Substrate Material on the Noise Characteristics of GaN HEMT

In this paper, the impact of AlGaN barrier thickness (tAlGaN) and substrate leakage on the noise conductance and noise figure in GaN High Electron Mobility Transistor (HEMT) is investigated. The investigation and analysis in this paper are targeting the Low Noise Amplifier (LNA) applications. The noise analysis is carried out using Technology Computer-Aided Design (TCAD) physical simulator. Initially, the DC, RF, and noise simulations are validated against measurements of a GaN device. AlGaN barrier thickness (tAlGaN) is varied and its impact on the minimum noise figure (NFmin) is analyzed. It is observed that the NFmin decreases with tAlGaN reduction at the typical bias conditions of LNA. This observation on the impact of tAlGaN on the NFmin follows Fukui&#x2019;s model, which states that the NFmin decreases with the increase in transconductance. In addition, the impact of the substrate material on noise performance is analyzed. The substrates used for the investigation are Silicon (Si) and Silicon Carbide (SiC). At 40 GHz, it is found that the noise conductance and the NFmin of GaN HEMT on SiC substrate is reduced by 13% and 12%, respectively, in comparison with GaN HEMT on Si substrate. This could be attributed to the lower gate-to-substrate capacitance of the GaN HEMT on SiC substrate.

Free-standing tantalum pentoxide waveguides for gas sensing in the mid-infrared

Typical applications of integrated photonics in the mid-infrared (MIR) are different from near-infrared (telecom) range and, in many instances, they involve chemical sensing through MIR spectroscopy. Such applications necessitate tailored designs of optical waveguides. Both cross-sectional designs and processing methods of MIR waveguides have been a subject of extensive research, where material transparency and substrate leakage of guided modes have been the most common challenges. Both these challenges can be solved simultaneously with air-suspended waveguides. In this paper, tantalum pentoxide (Ta2O5, tantala) thin films deposited on silicon were tested for two different dry under-etching procedures, XeF2 and SF6 plasma, with both of them facilitating selective removal of silicon. We analyze the advantages and limitations of these two methods and optimize the processing for fabricating membranes with arbitrary length and cross-sectional aspect ratio over 300. The performance of these high-aspect-ratio membranes as a framework for single-mode waveguides is rigorously analyzed at 2566 nm wavelength. With tantala being transparent up to 10 µm wavelength, such waveguides are particularly well suited for gas sensing in MIR.

Neuromorphic analog spiking-modulator for audio signal processing

While CMOS scaling is currently reaching its limits in power dissipation and circuit density, the analogy between biology and silicon is emerging as a solution to ultra-low-power signal processing. Urgent applications involving artificial vision and audition, including intelligent sensing, appeal original energy efficient and ultra-miniaturized silicon-based solutions. While state-of-the-art is focusing on digital-oriented solutions, this paper proposes a neuromorphic analog signal processor using Izhikevich-based artificial neurons in an analog spiking modulator. A varicap-based artificial neuron is explored reducing the silicon area to $$98.6\;\upmu{\text{m}}^{2}$$ and the substrate leakage to a $$1.95 \;{\text{fJ}}/{\text{spike}}$$ efficiency. Post-layout simulation results are presented to investigate the high-resolution, high-speed, and full-scale dynamic range for audio signal processing applications. The proposal demonstrates a $$9 \;{\text{bits}}$$ spiking-modulator resolution, a maximum of $$8\;{\text{fJ}}/{\text{conv}}$$ efficiency, and a root–mean–square error of $$0.63\;{\text{mV}}_{RMS}$$ .

(Invited) Directly Silicon Nitride Waveguide Coupled Ge Photodiode for Non-SOI PIC and Epic Platforms

A Ge photodiode, directly coupled to a silicon nitride waveguide, showing more than 67 GHz bandwidth is demonstrated. This paves the way for utterly new SiN waveguide platform based applications. By light feeding through SiN waveguides, the new photodiode can also be a key enabler for a bulk-Si based, monolithically integrated electronic-photonic integrated circuit platform. We show that the new devices, fabricated on bulk-Si, provide the same bandwidths as Si waveguide coupled SOI based reference Ge photodiodes. However, their O-band responsivity is 0.3 A/W, which is about three times lower compared to the SOI wave-guide coupled devices. We attribute this effect mainly to substrate leakage, being confirmed by simulations. We demonstrate that bulk-Si based diodes can be fabricated with high yield and low metrics tolerances.

Optimized Substrate for Improved Performance of Stacked Nanosheet Field-Effect Transistor

The recently proposed stacked nanosheet-field-effect transistor (SNSH-FET) is considered as a promising candidate for continued scaling with silicon. While using punchthrough-stopper-doped (or) ground-plane-doped silicon substrate (PTS-Si substrate) in which the top part of the substrate is doped heavily with the p-type (for nMOS) impurity to avoid punchthrough leakage between the source and the drain. The heavily doped p–n junction formed at the drain–substrate junction acts as a reverse-biased tunnel diode during ${V}_{{\text {DS}}}$ biasing, which leads to large substrate leakage current. We presented SuperSteep-Retrograde silicon substrate (SSR-Si substrate) configuration which reduces the tunneling current by increasing the tunnel barrier width and diminishing the peak electric field at the drain–substrate junction. The SSR-Si substrate is achieved by growing a lightly doped or undoped layer of silicon (SSR-buffer layer) on the PTS-doped substrate. The impact of SSR-buffer layer thickness is studied and the optimal thickness (12 nm) is presented. The vertically stacked channels’ configuration leads to position-dependent current densities in different channels due to position-dependent series resistance. Herein, we present nanosheet width optimization as a solution to achieve homogeneous current ratio between all the channels thereby resulting in better linearity performance. The self-heating and RF performance of the presented SSR-Si substrate is compared with the silicon-on-insulator (SOI) substrate. The results show that SSR-Si substrate can be a better substrate for SNSH-FET because of better self-heating performance.

High-efficiency end-fire 3D optical phased array based on a multi-layer Si3N4/SiO2 platform.

Beam-steering devices such as optical phased arrays (OPAs) are key components in the applications of solid-state Lidar and wireless communication. The traditional single-layer OPA results in a significant energy loss due to substrate leakage caused by the downward coupling from the grating coupler structure. In this work, we have investigated a structure based on a multi-layer ${\rm Si}_{3}{\rm N}_{4}/{\rm SiO}_{2}$Si3N4/SiO2 platform that can form a 3D OPA to emit light from the edge of the device with high efficiency; a 2D converged out-coupling beam will be end-fired to the air. High efficiency and wide horizontal beam steering are demonstrated numerically, and the influence of vertical crosstalk, delay length, and number of waveguide layers are discussed, as well as the fabrication feasibility.