Substrate Hot Electron Research Articles

New hot-carrier injection and device degradation in submicron MOSFETs

New kinds of hot-carrier injection mechanisms, which are different from channel hot-electron and substrate hot-electron injection mechanisms already reported by Ning, et al., are presented. These are first drain avalanche hot-carrier (DAHC) injection and secondly substrate current induced hot-electron (SCHE) injection. DAHC injection is due to the emission of electrons and holes heated in the drain avalanche plasma. SCHE injection is caused by the emission of excess electrons originating from impact ionisation of substrate current. The authors have succeeded in directly observing these two injection phenomena by measuring gate current as low as of the order of 10−15 A for small size MOS devices having effective channel length below 1.0 μm and gate oxide thinner than 10nm. The measured gate currents due to both injection mechanisms are also modelled numerically using the CADDET, a 2-D analysis program. In addition, device degradation due to these new injections is clarified. Base on the experimendal results, it is shown that DAHC effect rather than channel hot-electron effect, is more responsible for hot carrier related device degradation. The SCHC is also found to cause significant threshold shift, even at the VD<3V bias condition. thus, the presented injection phenomena prove to impose more Severe constraints on the submicron VLSI device design.

Sensitive technique for measuring small MOS gate currents

A simple but ultrasensitive method for measuring MOS gate currents down to the attoampere range has been developed. The new technique routinely measures oxide currents in conventional MOSFET structures arising from effects such as hot-electron emission, oxide leakage or tunneling at levels too low to be easily detected by previously available techniques. No FAMOS-type device is required. This technique was used to measure both channel and substrate hot-electron currents. Substrate hot-electron currents measured with the new technique were in excellent agreement with those measured directly.

Hot-electron emission in n-channel IGFETs

The authors discuss the emission of both substrate and channel hot electrons from the silicon into the gate insulator of n-channel IGFETs. In each case the discussion begins with a physical model to elucidate the many parametric dependencies. The effect of changing important material and geometrical parameters as well as temperature and terminal voltages is documented with emission data. Under proper conditions the majority of emitted hot electrons are collected at the gate electrode, so that electron heating can be studied by directly observing gate current. In addition, gate current is a sensitive probe of trapping effects in the gate insulator, and it is shown how these measurements can be used to deduce long-term stability in IGFET structures.

Hot-electron emission in N-channel IGFET's

This paper discusses the emission of both substrate and channel hot electrons from the silicon into the gate insulator of n-channel IGFET's. In each case the discussion begins with a physical model to elucidate the many parametric dependencies. The effect of changing important material and geometrical parameters as well as temperature and terminal voltages is documented with emission data. Under proper conditions the majority of emitted hot electrons are collected at the gate electrode, so that electron heating can be studied by directly observing gate current. In addition, gate current is a sensitive probe of trapping effects in the gate insulator, and it is shown how these measurements can be used to deduce long-term stability in IGFET structures.

1 µm MOSFET VLSI technology: Part IV—Hot-electron design constraints

An approach is described for determining the hot-electron-limited voltages for silicon MOSFET's of small dimensions. The approach was followed in determining the room-temperature and the 77 K hot-electron-limited voltages for a device designed to have a minimum channel length of 1 µm. The substrate hot-electron limits were determined empirically from measurements of the emission probabilities as a function of voltage using devices of reentrant geometry. The channel hot-electron limits were determined empirically from measurements of the injection current as a function of voltage and from long-term stress experiments. For the 1 µm design considered, the channel hot-electron limits are lower than the substrate hot-electron limits. The maximum voltage, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_{DS} = V_{GS}</tex> , is 4.75 V at room temperature (25°C) and 3.5 V at 77 K. More details of the voltage limits as well as the approach for determining them are discussed. Examples of circuits designed with these devices to operate within these hot-electron voltage limits are also discussed.

1 /spl mu/m MOSFET VLSI technology. IV. Hot-electron design constraints

For pt.III see ibid., vol.SC14, no.2, p.255 (1979). An approach is described for determining the hot-electron-limited voltages for silicon MOSFETs of small dimensions. The approach was followed in determining the room-temperature and the 77K hot-electron-limited voltages for a device designed to have a minimum channel length of 1 /spl mu/m. The substrate hot-electron limits were determined empirically from measurements of the emission probabilities as a function of voltage using devices of reentrant geometry. The channel hot-electron limits were determined empirically from measurements of the injection current as a function of voltage and from long-term stress experiments.

MOST capacitor memory : O. Enomoto and K. Ichijo, NEC Res. Dev., Japan No. 12, October (1968), p. 29

In order to obtain a reliable multi-bit/level operation for nano-scaled polycrystalline silicon-oxide-nitride-oxide-silicon (SONOS) memory, two different localized charge-injection programming methods, the channel hot electron injection with a positive substrate bias (CHEI-P) and pulse agitated substrate hot electron injection (PASHEI), are operated in 90 nm SONOS cells. It is found that the cells programmed by CHEI-P have the better endurance property than by PASHEI. The better endurance is due to the less accumulation of charges in the nitride layer, evidenced by surface potential profiling technique. CHEI-P program further exhibits the superior endurance and retention properties after 104 program/erase cycles in 4-bit/4-level operations. These results illustrate that CHEI-P program is a promising candidate for multi-bit/levels nano-sized SONOS memory.