Substrate Coupling Effects Research Articles

A Broadband and Scalable On-Chip Inductor Model Appropriate for Operation Modes of Varying Substrate Resistivities

A broadband and scalable model is developed to accurately simulate on-chip inductors with various dimensions and substrate resistivities. The broadband accuracy is proven over frequencies of up to 20 GHz, even beyond resonance. A new scheme of resistance-inductance-capacitance networks is deployed for the spiral coils and substrate to account for 3-D eddy current, substrate return path, and spiral coil to substrate coupling effects. The 3-D eddy current is identified as the key element essential to accurately simulate the broadband characteristics. Electromagnetic simulation using the Advanced Design System momentum is conducted to predict the on-chip inductor performance corresponding to a wide range of substrate resistivities(PSi = 0.05-1 KOmega ldr cm) ldr Three operation modes such as transverse electromagnetic mode, slow-wave mode, and eddy current mode are reproduced. The model parameters manifest themselves as physics-based through relevant correlation with PSi over three operation modes. The onset of slow-wave mode can be consistently explained by a key element Rp introduced in our model, which accounts for the conductor loss due to an eddy current arising from magnetic field coupling through a substrate return path. This broadband and scalable model is useful for radio frequency circuit simulation. In addition, it can facilitate an optimum design of on-chip inductors through the physics-based model parameters relevant to varying substrate resistivities.

Dynamic models for substrate coupling in mixed-mode systems

In modern monolithic integrated circuits, substrate coupling is a major concern in mixed-mode systems design. Verification of such systems implies the availability of accurate and simulation-efficient substrate coupling models. Traditionally, for frequencies up to a few gigahertz, pure resistive models have been considered sufficient. However, with increasing frequencies of operation, dynamic models become mandatory. The authors motivate the use of dynamic resistive-capacitive (RC) models of substrate coupling as a natural extension to the standard purely resistive models. They propose an extraction methodology that starts with information about the process parameters and circuit's contact layout, and leads to a contact-to-contact RC element model. The underlying algorithm is based on a finite difference discretisation of the substrate, leading to a large tridimensional mesh which is reduced by means of a fast multigrid algorithm. Unlike standard model order reduction algorithms which can produce models of similar accuracy to state-space descriptions, the proposed method leads to a realisable RC model that can trivially be incorporated into circuit simulation tools. As a first approximation, such a model is shown to correspond to a single time-constant system. Furthermore, it is shown that this time constant can be computed from knowledge of the conductivity and permittivity of a single dominant layer. It is verified that this formulation can accurately model substrate coupling effects for frequencies up to several tens of gigahertz.

Performance comparison of substrate coupling effect between silicon and SOI substrates in RF-CMOS technology

Substrate coupling may severely degrade the electrical performances of high-speed and RF integrated circuits. An isolation technique study of parasitic effects due to substrate coupling between two blocks of integrated circuits in an RF CMOS 90 nm technology is presented. Isolation performances are compared for both bulk silicon (Si) and silicon-on-insulator (SOI) substrate. For every substrate, a compact electrical model matching well with measurement results is proposed for test structures composed of 50×50 µm cells surrounded with an appropriate guard ring. An isolation improvement of 10 dB is reached by an additional P-type guard ring placed around one cell and an isolation level of 45 dB is achieved at 1 GHz for bulk Si substrate.

Modeling Techniques and Verification Methodologies for Substrate Coupling Effects in Mixed-Signal System-on-Chip Designs

The substrate noise coupling problems in today's complex mixed-signal system-on-chip (MS-SOC) brings a new set of challenges for designers. In this paper, we propose a global methodology that includes an early verification in the design flow as well as a postlayout iterative optimization to deal with substrate noise, and helps designers to achieve a first silicon-success of their chips. An improved semi-analytical modeling technique exploiting the basic behaviors of this noise is developed. This method significantly accelerates the substrate modeling, avoids the dense matrix storage, and, hence, enables the implementation of an iterative noise-immunity optimization loop working at full-chip level. The integration of the methodology in a typical mixed-signal design flow is illustrated and its successful application to achieve a single-chip integration of a transceiver is demonstrated.

RF integrated systems

This article will detail the advantages and the draw back of the monochip approach for the system integration, the process selection (CMOS or BiCMOS), and the needed knowledge to perform a successful design. A BiCMOS monochip, RF to digital base band on DCS1800 standard will be presented. This circuit has been designed in order to underline the substrate coupling effects. Linked to this design, a substrate coupling study will be developed. A low cost CMOS zero IF Bluetooth RF front end design will be detailed, this approach is defined in order to integrate the global RF and Base Band functions in a monochip.

A four-step method for de-embedding gigahertz on-wafer CMOS measurements

In this paper, a de-embedding method is proposed for conducting accurate on-wafer device measurements in the gigahertz range. The method addresses issues of substrate coupling and contact effects and is therefore suitable for measurements with lossy technologies such as CMOS. The method assumes a probe-tip two-port calibration performed with well-known techniques and impedance substrates. By employing a physical interpretation of the test-fixture, the method alleviates a number of known problems with common de-embedding procedures. Four distinct mathematical steps are suggested to de-embed parasitics for the test-fixture to give an accurate measurement of the device under test. By introducing a simple compensation factor for in-fixture standard imperfections, the proposed method allows large devices to be measured with high accuracy. The applicability of the method is demonstrated with measurements up to 12 GHz.

A High-Frequency MOS Transistor Model and its Effects on Radio-Frequency Circuits

Accurate modeling and efficient parameter extraction of a small signal equivalent circuit of MOS transistors for high-frequency operation are presented. The small-signal equivalent circuit is based on the quasi-static approximation which was found to be adequate up to 10 GHz for MOS transistors fabricated by a 20 GHz cutoff frequency technology. The extrinsic components and substrate coupling effects are properly included. Direct extraction is performed by Y-parameter analysis on the equivalent circuit in the linear and saturation regions of operation. A low-noise amplifier is used to illustrate the effects on circuit performance due to accurate inclusion of extrinsic components in the model. Good agreement between simulated results and measured data on high-frequency transistor characteristics has been achieved.

Efficient techniques for accurate modeling and simulation of substrate coupling in mixed-signal IC's

Industry trends aimed at integrating higher levels of circuit functionality have triggered a proliferation of mixed analog-digital systems. Magnified noise coupling through the common chip substrate has made the design and verification of such systems an increasingly difficult task. In this paper we present a fast eigendecomposition technique that accelerates operator application in BEM methods and avoids the dense-matrix storage while taking all of the substrate boundary effects into account explicitly. This technique can be used for accurate and efficient modeling of substrate coupling effects in mixed-signal integrated circuits.

Process alternatives and scaling limits for high-density silicon tactile imagers

Abstract In this paper the process complexities and parasitic substrate coupling effects are compared for several different high-density capacitive tactile imagers. The dissolved-wafer process using diffused bulk-silicon row lines and metal-on-glass columns is found to offer the simplest process and fastest response, requiring only five non-critical masks and producing a settling time for the column charge of about 1 μs. Using this process, a 1024-element array with a force range of 1 gm and a spatial resolution of 500 μm produces a force resolution equivalent to seven bits. Scaled to a 4096-element array, this same process should produce a force resolution of nearly six bits for the same force range and a spatial resolution of 250 μm.