Substrate Bias Generator Research Articles

Atomic Layer Etching of GaN and AlGaN Using CH4/H2, H2 and HCl Chemistry

Modern microelectronic components for high-power and high-frequency applications require reliability and reproducibility of the production processes. Atomic layer etching (ALE) represents a key technology for achieving these requirements.An ALE sequence is characterized by a chemical modification step that affects only the top atomic layer of the surface (adhesion) and an ion assisted non-reactive inert gas etching step that removes only this chemically modified area due to creation of volatile byproducts. These two steps are separated by inert gas purge. This grants the etching of single atomic layers. The etching step can be triggered by thermal energy or kinetic energy by impinging particles (e.g. ion bombardment by a plasma). The low energy required for ALE guarantees low-damage etching.In literature ALE processes using Cl2 are often reported. In this work, the results of plasma-enhanced ALE of GaN and AlGaN using different chemistries of CH4/H2, H2 and HCl as etch gases are presented. The experiments were performed with a highly customized etch facility equipped with a capacitively coupled plasma source (CCP, 60 MHz) and a substrate bias generator (RF, 2 MHz). The investigations were carried out on epitaxially deposited GaN on sapphire with masks of protective resist and SiO2 as well as GaN-AlGaN heterostructures with patterned SiO2 maskings. For process analysis optical emission spectroscopy (OES) was carried out. The etching rate and roughness were determined by ellipsometry and atomic force microscopy (AFM) as well as scanning electron microscopy (SEM).Observations by OES indicate a successful excitation and dissociation of the etching molecules. With rising plasma powers physical sputtering effects were revealed. At the beginning of the process development continuous etching processes were examined. With CH4/H2 chemistry using GaN samples it was found that the etching behavior is strongly influenced by the type of masking material. Protective resist resulted in a low etch rate of 7.5 nm/min and significant damage of the masking material. The cause of this behavior is assumed to be redeposition of material by interaction of methane, resist, and plasma. With the change to a hard mask of SiO2 etch rates of 45 to 72 nm/min were achieved, increasing with RF-power and CH4/H2 ratio. Adding methane led to detrimental side effects such as dendrite growth and wall formation on the transient region of unmasked to former masked sample areas. In the further development of the ALE process an etch chemistry using only hydrogen as the chemical etchant was used resulting in an etch per cycle (EPC) of about 3 Å for GaN samples. Further investigations of ALE with hydrogen etch chemistry on GaN-AlGaN samples revealed that AlGaN, in contrast to pure GaN, could not be etched successfully with this chemistry.Substituting CH4/H2 or H2 to HCl enables the etch of AlGaN. The investigations carried out indicate that this etching process is also a self-limiting ALE. AFM measurements revealed an EPC of 1.2 Å for lower RF-powers (50 W). Increasing the RF power to 150 W only slightly enhance the EPC to 2.0 Å. The surface roughness tends to decrease with rising RF-power from 50 to 300 W.

Substrate currents in short buried-channel PMOS devices at cryogenic temperatures

For MOSFETs biased in the saturation mode, measurable substrate current due to impact ionization near the drain often flows. If this substrate current is large enough, the substrate bias generator can become overloaded and breakdown can occur if the source - substrate junction is forward biased. Substrate currents can also be used as a reliability monitor of hot carrier effects in short channel MOS devices. In this paper, detailed experimental results are presented on the variation of peak substrate currents in short buried-channel PMOS devices from their I DS– V GS curves at varying substrate and drain biases, at temperatures between 77 and 300 K. From the experimental results, an empirical curve-fit model of the peak substrate current normalized to the drain current and for a constant drain bias was found to be / P,SUB// DS≈α(T, V BS)L -β(T, V BS) Numerical values for the functional dependence of α and β are determined. Detailed results on these functional dependences on temperature and bias voltages are reported.

A latch-up-like new failure mechanism for high-density CMOS dynamic RAMs

A latch-up-like failure phenomenon that shows hysteresis in the V/sub cc/-I/sub cc/ characteristics observed in a high-density CMOS dynamic RAM that utilizes an on-chip substrate-bias generator is discussed. This failure is caused by large substrate-current generation due to the depletion-mode threshold voltage of n-channel transistors at near-zero substrate-bias operation. It is increasingly important not only to design a powerful substrate-bias generator but also to suppress the back-gate bias effect on the n-channel transistor.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An optimized design for high‐performance megabit DRAMs

AbstractActual guidelines for the techniques to be employed for high‐performance megabit DRAMs have been studied based on the performance analysis of conventional NMOS 1MDRAMs. It was found that for reduction of access time, use of word line Al shunt method + polycide bit line system based of three‐layered poly‐silicon process, reduction of I/O line capacitance and use of CMOS current mirror‐type preamplifier are effective. For reduction of current consumption, 1/2 Vcc precharge of bit lines, 1/2 division operation of memory arrays, and use of CMOS process are confirmed to be effective. For battery backup, reduction of standby current was considered. It was found that intermittent operation of substrate bias generator is effective. For further improvement, use of LDD transistors is needed in which twin wells with divided wells are presumed.Based on the forementioned studies, CMOS 1MDRAMs were fabricated. The RAS access time at 5 V and 25°C was 50 ns with the current consumption of 28 mA (tc = 260 ns). Since the average standby current at refresh interval of 64 ms was 80 μA, battery backup is sufficiently possible in this high‐performance 1MDRAM.

Accurate measurement of the operating frequency in ICs with the SEM

Unknown frequencies of integrated-circuit interconnections are measured with an accuracy of 1 Hz by an extension of the frequency mapping proposed by Brust and Fox (1984, 1985). The oscillation frequency of a substrate bias generator in a 1M DRAM is measured as a function of the supply voltage.

A 25-ns 16K CMOS PROM using a four-transistor cell and differential design techniques

A 25-ns, 250-mW, 2K/spl times/8 PROM using a 1.2-/spl mu/m n-well CMOS technology is described. Speed and programmability are optimized by separating the READ and WRITE transistor functions in a four-transistor differential cell and using differential design techniques. For the first time, a substrate bias generator is used in an EPROM technology to improve speed and raise latch-up immunity to over 200 mA.

A temperature- and process-tolerant 64K EEPROM

A 64K EEPROM is described with emphasis on the circuit techniques used to achieve extended temperature operation. The core architecture is considered and a suitable byte layout which eliminates possible punchthrough in the memory cell is shown. A feedback-controlled substrate bias generator is described which delivers -1.0 V/spl plusmn/0.05 V and reduces significantly field transistor leakages. In addition, a /spl plusmn/1% stable voltage reference is shown to accurately control the programming voltage for the memory array to 20 V/spl plusmn/1 V over the full military temperature range (-55/spl deg/-+125/spl deg/C) and /spl plusmn/10% power-supply variation. A process-insensitive write timing pulse trimmed by E2 fuses is discussed, as is the PAGE-MODE WRITE circuitry in relation to the bitline latches.

A monolithic 64 bit floating-point coprocessor

A double/single-precision floating-point processor using a titanium disilicide 3.5-/spl mu/m NMOS process achieves double-precision add/subtract, multiply, and divide in 2, 8, and 16 /spl mu/s respectively. The chip has about 35K devices and is about 400 mil on the side. The chip uses a single 5-V supply with TTL-compatible levels on all signals except for the clocks, which require 4.5 V for a logic high. Four input clocks are used to generate eight 50-ns intervals. A -2.5 V substrate bias generator is designed on the chip but uses a pin for an external capacitor. The processor, which is to be used in a desktop implementation of a minicomputer, executes the floating-point instruction set for the micro-Eclipse computer.

A fault-tolerant 30 ns/375 mW 16Kx1 NMOS static RAM

A fault-tolerant 30950 mil/SUP 2/ (19.9 mm/SUP 2/) 16K/spl times/1 static MOS RAM has been fabricated with a single polysilicon E/D NMOS process. Using circuit techniques normally restricted to dynamic RAMs, but adapted for asynchronous operation, the device achieves a typical access time of 30 ns while dissipating only 375 mW. Among the topics discussed in a new single-polysilicon memory cell configuration, the first truly asynchronous bootstrap circuit, an active bit-line equilibration and precharge scheme, and a new power-efficient substrate bias generator. Also described is an on-chip redundancy scheme which consumes approximately 2 percent of the total chip area, does not compromise access time and can be programmed using standard test equipment.

A 50 ns 4K static DSA MOS RAM

An advanced DSA MOS (DMOS) technology is discussed as it applies to a high-speed 4K bit semiconductor static memory. It uses a polysilicon gate length of 4 /spl mu/m, a gate oxide thickness less than 800 /spl Aring/, and a shallow junction depth (<0.6 /spl mu/m) using conventional photolithographic methods. With these features, the effective channel length of the DSA MOST was reduced to 0.5 /spl mu/m and a smaller junction capacitance was obtained by the use of a high-resistivity (100-200 /spl Omega/.cm) substrate without a substrate bias generator. Combined with the depletion load transistors and selective oxidation processing, a static RAM of 50 ns access time at 630 mW power dissipation, die size of 5.24/spl times/5.36 mm/SUP 2/, and cell size of 53/spl times/62 /spl mu/m/SUP 2/ was obtained.