Submicron Process Research Articles

High-Q SAW filter and submicron process technology for timing extraction in high bit rate optical communications system

A new surface acoustic wave (SAW) filter configuration that consists of 3/spl lambda//8-wide meander-type electrodes and 3/spl lambda//8-wide excitation electrodes on ST-cut quartz was designed for use in a 2.5-Gb/s optical communications system. New submicron process techniques using the phase shifting method as well as several types of resist were investigated to fabricate this filter. It had an insertion loss of less than 14 dB and a Q of about 700, and satisfied all required system specifications over a temperature range from 0 to 60/spl deg/C.

Steam Laser Cleaning of Plasma-Etch-Induced Polymers from Via Holes

As the wafer industry enters into submicron processes and below, the demand for new cleaning technology after plasma etching increases. The cleanliness of via holes becomes very crucial for the success of low-resistance interconnecting high-density ultra-large-scale integrated devices. In this study, a relatively new approach in removing the sidewall and bottom polymers resulting from reactive ion etching of via holes, using dry and steam laser cleaning techniques is investigated. The presence of a layer of isopropanol (IPA) film on the wafer surface during excimer laser irradiation is found to improve the removal efficiency greatly even at fluences as low as 80–100 mJ cm-2–much lower than the damage threshold of the underlying Al–Cu metal film with titanium nitride anti-reflective coating of 250–280 mJ cm-2. The explosive evaporation of IPA and the creation of bubbles at the liquid-substrate interface were proposed to be the reason for the improvement. Experimental results show however that the presence of a layer of acetone film does not improve but even impedes the laser cleaning process. An explanation is offered for this phenomenon in terms of the difference in the absorbance of the two liquids at the laser wavelength.

Laser cleaning of etch-induced polymers from via holes

The demand for new wafer cleaning technology after plasma etching increases as the industry enters into submicron processes. The success of low-resistance interconnecting high-density ultralarge-scale integrated devices depends on the cleanliness of via holes. A new approach in removing the sidewall and bottom polymers resulting from reactive ion etching of via holes, using a noncontact dry laser cleaning technique is reported and investigated in this study. Pulsed excimer laser irradiation at 248 nm is found to be capable of removing the polymers by subthreshold ablation, even at fluences limited by the damage threshold of the underlying Al–Cu metal film with titanium nitride (TiN) antireflective coating of 250–280 mJ cm−2. The various mechanisms possibly involved in the laser removal of the via-etch-induced polymer below its ablation threshold are discussed. Experimental results also show that the ablation rate when irradiating at an angle is not only comparable to that at vertical incidence, but even register higher values for most of the ablation rate data obtained. Thus the performance in terms of ablation rate does not slacken when the incident radiation is done at an angle to expose the sidewall polymers of the via holes to laser irradiation. Comparing ablation results obtained using Nd-YAG laser and excimer laser shows that although the shorter 7 ns Nd-YAG laser pulse gives a greater etch thickness than the 23 ns excimer laser pulse, it also tends to damage the metal films and the silicon substrates of the via wafers more easily. The damage threshold using the third and fourth harmonics of the Nd-YAG laser at 355 and 266 nm was just above 100 mJ cm−2 after 20 pulses.

Design methodology and optimization of gate-driven NMOS ESD protection circuits in submicron CMOS processes

This paper describes the design methodology for gate driven NMOS ESD protection in submicron CMOS processes. A new PNP Driven NMOS (PDNMOS)-protection scheme is presented. Without requiring any additional process steps or introducing any additional impedance in signal path, the PDN-MOS is effective even for small analog/mixed-signal designs. SPICE simulations are used to optimize the design. High ESD performance of the PDNMOS protection in both nonsilicided and silicided submicron processes is demonstrated in this work.

Critical interconnects specifications for LP/LV integrated circuits: interconnections and packaging trends

The multimedia and advanced telecommunications applications, such as Asynchronous Transfer Mode, inter-networking/ multicast protocols strongly drive technology improvements. The continuos progress of CMOS technology, allowing an extraordinary increase in integration density, raises the interconnect issue: in deep submicron processes interconnections have become a dominating factor in determining system performance. The paper analyzes the impact of high speed interconnections on system performance. The evolution of the integrated circuits, that are becoming more and more complex in terms of speed, number of I Os , requires the mastering of effective packaging and assembling technique for fulfilling the systems requirements. A survey of packaging technologies and advanced interconnect techniques is presented.

Novel ferroelectric epitaxial (Ba,Sr)TiO/sub 3/ capacitor for deep sub-micron memory applications

A novel ferroelectric capacitor cell was developed using a (Ba,Sr)TiO/sub 3/ (BSTO)/SrRuO/sub 3/ (SRO) heteroepitaxial technique on Si and strontium titanate substrates. Distinct ferroelectricity results from the c-axis being elongated due to lattice mismatch between the dielectric and electrode. The epitaxial BSTO capacitor showed distinct ferroelectricity even at 30 nm thickness, which is the thinnest ferroelectric film so far. Its superior ferroelectric properties, reliability, and sub-micron silicon process compatibility were confirmed.

A CMOS "soft-switched" transconductor and its application in gain control and filters

This paper presents a transconductor suitable for implementation in submicron CMOS technology. The transconductor is nearly insensitive for the second-order effects of the MOS transistors, which become more and more prevalent in today's submicron processes. The transconductor relies on a differential pair with variable degeneration resistance, while the degeneration resistors are soft-switched by means of MOS transistors. The transconductance is continuously tunable. A transconductor, using a device in which the degeneration resistors and soft switches are merged, is optimized for a maximum tuning range and can be used in variable gain stages like in an automatic gain control (AGC) circuit. Besides, a third-order 5.5 MHz low-pass filter has been realized in a 0.5-/spl mu/m CMOS process using the soft-switched transconductor. At a 3.3 V supply voltage the filter dissipates 12 mW and the dynamic range equals 62 dB where the total harmonic distortion (THD) is -48 dB for an input voltage of 1 Vpp.

Evolution of magnetic microstructure in high-coercivity permanent magnets imaged with magnetic force microscopy

Magnetic force microscopy (MFM) has been shown to give high-resolution imaging of magnetic domain structures in a variety of high-coercivity permanent magnets [Folks et al., J. Magn. Magn. Mater. (in press)]. We show that this technique can be extended by the application of external fields during imaging, thus allowing direct observation of submicron microstructural evolution as a function of field. Electromagnets mounted on the MFM supplied fields up to 7 kOe laterally and 3 kOe vertically. In sintered materials, submicron processes such as depinning of domain walls at grain boundaries, domain fragmentation, and hysteresis were observed. MFM tips having very low coercivity highlighted domain walls, whereas higher-coercivity tips suffered unpredictable rotation of their magnetic moment due to both the sample and applied fields, leading to images which are difficult to interpret. For imaging of the finer-grained melt-quenched magnets, however, relatively high-coercivity tips were superior. These results show promise for the direct observation of the submicron-scale processes that dictate bulk magnetic properties, and the quantification of their field dependence.

Submicron processing of InAs based quantum wells: A new, highly selective wet etchant for AlSb

We describe a processing technology for patterning InAs/AlSb heterostructures far in the submicron regime. The processing is based on a new, highly selective wet etchant for AlSb. We discuss the electrical characterization of narrow ballistic channels (down to ≈140 nm width) realized with present technology, and demonstrate that the processing preserves the high mobility of the material.

Movable microstructures made by a sub-micron LIGA process

Movable microstructures made by a sub-micron LIGA process

Accurate simultaneous switching noise estimation including velocity-saturation effects

Simultaneous switching noise (SSN) on power supply lines is caused by the large switching transient currents flowing through parasitic inductances at the chip-package-pin interface. A new expression to estimate SSN in CMOS circuits that includes the velocity saturation effects seen in the short-channel MOSFETs is derived. SPICE Level 3 simulation results show that the formula predicts the SSN more accurately as compared to existing approaches for submicron processes even at reduced supply voltages.

Simulation of the image reversal submicron process in integrated circuit fabrication

An algorithm for the simulation of the image reversal process based on Cellular Automata is presented for the first time. The development resist profiles produced by this algorithm are of the same geometry and shape as those obtained by experiments. Furthermore, the dependence of the slope of a resist-line-edge on the bake time has also been successfully reproduced using this algorithm.

CMOS tunable linear current divider

A CMOS current divider is proposed which can handle an input current as large as the bias current, i.e. the modulation depth can be 100%;. The performance of the circuit is nearly independent of transistor characteristics. Therefore the circuit is well applicable for designs in modern submicron processes. The measured divider can be tuned over more than a factor of 2

Use of short-loop electrical measurements for yield improvement

Modern submicron processes are more sensitive to both random and systematic wafer-level process variation than ever before. Given the dimensional control limitations of new technologies, the amount of wafer-to-wafer and within wafer nonuniformity of many steps is becoming a significant fraction of the total error budget, which already includes the usual step-to-step allocations. However, a significant portion of the total observed variability is systematic in nature. Accordingly, particle defects may not continue to dominate parametric yield loss without improved understanding of parametric variations. In this paper, we demonstrate the use of short-loop electrical metrology to carefully characterize and decouple wafer-level variability of several critical processing steps. More specifically, we present our method and give results obtained from variability analyses for lithography critical dimension (CD) and inter-level dielectric (ILD) thickness control. Using statistically designed experiments and dedicated test structures, the main factors affecting dielectric thickness variability has been identified. The systematic variability from a wafer stepper has been extracted using a physically based statistical data filter. Once isolated, the deterministic variability can be modeled and controlled to enhance process and circuit design for manufacturability (DFM). We hope that in the future this work will be coupled with novel DFM-oriented CAD tools that encapsulate this information in a fashion that makes it useful to process and circuit designers. >

Movable microstructures made by a sub-micron LIGA process

Movable microstructures with high aspect ratios were made with lateral dimensions down to the sub-micron domain by the LIGA process and a sacrificial layer technique. Compared to microstructures usually made by LIGA, all dimensions were reduced approximately by a factor of 10, while the aspect ratio was kept constant. The smaller resist thickness in the range of some ten micrometers allowed much lower X-ray doses and energies to be used for exposure and the absorbers with a thickness of only 3 μm to be employed. As the lateral dimensions are smaller, a much larger number of devices can be fabricated in one batch. Therefore, the production costs of deep etch X-ray lithography are reduced dramatically. Electrostatic linear actuators with lateral dimensions as small as 500 nm were manufactured to demonstrate the advantages of LIGA in sub-micron dimensions. An X-ray mask with absorbers 2.8 μm high was produced by a three-level technique. The linear actuators consisted of several arrays of capacitor plates combined into an electrostatic driving unit with an active area, typically, 0.3 mm2 and less. The driving unit was supported by folded beam flexures to avoid frictional forces. They also guaranteed parallel movement of the capacitor plates. The functionality of these devices was demonstrated by measuring displacement as a function of the voltage applied.

Ultra High-Speed Optical Parallel Interconnections.

Present paper describes a transmission data format, called “Group Multiplexing and Coding, ” for ultra high-speed optical parallel interconnections and related devices. The potentiality of the format for solving skew and burst-mode compatibility problems is also presented.Our optical transmitter and receiver modules comprises a semiconductor laser diode arraywith a low threshold current, a photodiode with ultra-low parasitic capacitance, and arrayed LSICs fabricated by a GaAs submicron process. A 156 Mb/s-20 channel parallel transmissionexperiment over 400m shows that our transmission format solves skew and burst-mode compatibilityproblems in ultra high-speed optical transmissions.

Contact and via structures with copper interconnects fabricated using dual Damascene technology

A novel submicron process sequence was developed for the fabrication of CoSi/sub 2//n/sup +/-Si, CoSi/sub 2//p/sup +/-Si ohmic contacts and multilevel interconnects with copper as the interconnect/via metal and titanium as the diffusion barrier. SiO/sub 2/ deposited by plasma enhanced chemical vapor deposition (PECVD) using TEOS/O/sub 2/ was planarized by the novel technique of chemical-mechanical polishing (CMP) and served as the dielectric. The recessed copper interconnects in the oxide were formed by chemical-mechanical polishing. (dual Damascene process). Electrical characterization of the ohmic contacts yielded contact resistivity values of 10/sup -6//spl Omega/-cm/sup 2/ or less. A specific contact resistivity value of 1.5/spl times/10/sup -8//spl Omega/-cm/sup 2/ was measured for metal/metal contacts.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

System-integration features and development tools key to FPGA design

The Xilinx XC4000 family of field programmable gate arrays (FPGAs) features a third-generation architecture implemented with a sub-micron process technology, resulting in up to twice the density and performance of the prior generation of devices. Advanced system integration features allow many varying system functions to be incorporated within the XC4000 FPGAs, further increasing system performance and density. These advances in FPGA component technology have been matched by equally dramatic improvements to the CAE development tools. A design example illustrates how these advanced device features and software tools are applied in a system-level application.

On the use of DC measurements for ESD‐related process monitoring

AbstractDC measurements and transmission line method measurements have been carried out on field oxide NMOSTs made in a 0‐8 μm CMOS process. Analysis shows that DC measurements can be applied for fast ESD related feedback to submicron process development.

Research accomplishments at the University of Arizona SEMATECH Center of Excellence for contamination/defect assessment and control

The Arizona SEMATECH Center of Excellence (SCOE) was established in May of 1988, is funded by SEMATECH and contractually monitored by the Semiconductor Research Corporation (SRC). The SCOE is engaged in research in a broad front to understand and control contamination which causes yield limiting defects in submicron ULSI circuits. Sandia National Laboratory personnel are integrated with UA personnel in the SCOE research. The focus of the research is on contaminants, both particulates and homogeneous or distributed, which originate in, are caused by, or are transported and deposited by process gases and chemicals or process equipment. Further, the work involves investigating the mapping from contaminants and contaminant levels to degradation of device properties. The resulting degradation in device properties can then be used to estimate the effects of such contaminants for submicron processes and circuits. Results achieved during the four years of the SCOE's existence are described in this paper. >