Submicron Process Research Articles

Shift Left Quality Management System (QMS) Using a 3-D Matrix Scanning Method on System on a Chip

System-on-chip (SoC) quality management technology has been applied for a long time. During mass production, process defects and functional defects can have fatal consequences. However, in an SoC employing a high-coverage scan methodology, information from scan diagnostics can be used to locate failures and perform physical failure analysis (PFA) to improve production processes. PFA improves the overall production yield and leads to better quality control. However, since it is developed with deep sub-micron (DSM) processes, its complexity is high. It is difficult to accurately analyze data by merely collecting information from a single sample. PFA also involves high complexity associated with physical de-capping and analysis. To analyze all scan fail information, it is important to know which defect is the most critical and thus takes precedence. This has a large impact on the time to market, enabling the entire mass production process. In this brief, a 3D matrix scanning method is proposed, which can monitor product quality in real time during mass production. Using a quality management system, the results of two years of mass production have been shared. The problems encountered and the solutions to overcome these challenges during mass production have also been explained.

Order Statistics Based Low-Power Flash ADC with On-Chip Comparator Selection

High-speed flash ADCs are useful in high-speed applications such as communication receivers. Due to offset voltage variation in the sub-micron processes, the power consumption and the area increase significantly to suppress variation. As an alternative to suppressing the variation, we have developed a flash ADC architecture that selects the comparators based on offset voltage ranking for reference generation. Specifically, with the order statistics as a basis, our method selects the minimum number of comparators to obtain equally spaced reference values. Because the proposed ADC utilizes offset voltages as references, no resistor ladder is required. We also developed a time-domain sorting mechanism for the offset voltages to achieve on-chip comparator selection. We first perform a detailed analysis of the order statistics based selection method and then design a 4-bit ADC in a commercial 65-nm process and perform transistor-level simulation. When using 127 comparators, INLs of 20 virtual chips are in the range of -0.34LSB/+0.29LSB to -0.83LSB/+0.74LSB, and DNLs are in the range of -0.33LSB/+0.24LSB to -0.77LSB/+1.18LSB at 1-GS/s operation. Our ADC achieves the SNDR of 20.9dB at Nyquist-frequency input and the power consumption of 0.84mW.

Front-end electronics for silicon strip trackers: Architectures and evolution

Tracking detectors based on segmented semiconductor sensors have been present in high-energy physics experiments for more than 40 years. The development of these sensors was always strongly linked to advances in CMOS technologies that offer features supporting the design of specialized ASICs for readout purposes. While in the beginning, the front-end electronics only provided simple signal reception and amplification, sending out the raw analog data, growing demands from the experiments lead designers to begin directly integrating more advanced features for data processing and storage, power management, calibration functions, amongst others, on-chip. This development was, and continues to be, possible due to CMOS technology evolution, in particular the scaling. Besides higher speed and better transconductance, today’s sub-micron processes offer intrinsic ionizing radiation tolerance which, together with Single Event Effect (SEE) hardening techniques, allows design for reliable operation in a harsh radiation environment. Despite the enhanced functionality and greater number of transistors, higher time resolution and, in consequence, faster analog shaping and readout speed, the power consumption of typical front-end electronics measured per area of tracking detector remains of the order of a few tens of mW per square centimeter. The basic architecture of the input stage has also remained practically the same over the last 40 years. The optimal solution providing wide bandwidth and high open-loop gain at minimum power is the cascode: a cascade of common-source and common-gate amplifiers. Although each particular implementation differs slightly depending on the specific requirements and process used, the core of the preamplifier remains the same since its conception.

An input controlled leakage restrainer transistor‐based technique for leakage and short‐circuit power reduction of 1‐bit hybrid full adders

SummaryThe sharp increase in the leakage part of the total power of the very large scale integration (VLSI) circuits is a significant concern in the deep submicron CMOS process. The NOT gates, Gate Diffusion Input (GDI) cells, restorer NMOS–PMOS transistors for full‐swing operation, and any path from the power voltage to the ground are the main sources of leakage power dissipation as well as short‐circuit in the VLSI CMOS circuits/chips. The input controlled leakage restrainer transistor (ICLRT) is a new circuit‐level method that is proposed in this paper. The ICLRTs can be deliberately added to any VLSI CMOS circuit to largely diminish the total power dissipation especially by the reduction of its leakage and short‐circuit parts. The full adders are vital parts in various VLSI circuits/systems, especially in circuits used for fulfilling arithmetic operations. Those are often placed in the critical paths for multiplication and division, so influence the throughout the efficiency of the system. To test the proposed technique, ICLRTs added to five best 1‐bit hybrid full adders in the deep submicron process to fit the needs of the day. The efficiency of the proposed method is evaluated using SPICE simulations in 22‐nm CMOS BSIM4 process. Evaluation outcomes with 1‐V power supply verified that the power dissipation and power‐delay product (PDP) of the hybrid full adders based on ICLRT technique relative to corresponding original designs are reduced 65.67–95.7% and 35.85–87.37%, respectively. Mismatch analysis and Monte Carlo simulations prove the robustness and stability of the presented circuits in the presence of the process, voltage, and temperature (PVT) variations.

Reliability Enhanced Heterogeneous Phase Change Memory Architecture for Performance and Energy Efficiency

Next-generation memories have been actively researched to replace the existing memories like DRAM and flash in deep sub-micron process technology. Unlike the conventional charge-based memories, next-generation memories utilize the resistive properties of different materials to store and read a data. Among the next-generation memories, Phase Change Memory (PCM) is seen as a good choice for future memory systems, given its good read performance, process compatibility and scaling potential. To enhance the storage density, multi-level cell (MLC) operation is seemed promising which can store more than one bit in each PCM cell. However, MLC operation significantly degrades the reliability of PCM, thus requiring a strong Error Correction Code (ECC) to guarantee correct memory operation. The use of heavyweight ECC comes at cost of significant degradations in storage density, performance and energy efficiency. In this article, we propose a heterogeneous PCM architecture which uses both multi-level cell and single-level cell (SLC) together for a single word line. With highly-reliable SLC cells, the overall array reliability is enhanced. To improve the reliability further, a dynamic self-encoding/decoding scheme is performed before the data is written to the PCM cells. The dynamic scheme automatically determines the locations of MLC and SLC cells and sets the corresponding resistance levels to be programmed. Since the proposed encoding/decoding scheme does not require any additional stages or storages for encoding and decoding, the overhead is negligible. The improved reliability allows to use lighter ECC scheme which in turn helps to improve performance and energy efficiency of the MLC PCM. The experimental results show that the reliability is improved by approximately <inline-formula><tex-math notation="LaTeX">$10^6$</tex-math></inline-formula> times compared to the conventional 4LC and more than <inline-formula><tex-math notation="LaTeX">$10^3$</tex-math></inline-formula> times compared to the existing encoding methods. The performance improvement is 21.5 percent over the conventional 4LC and is more than 4.1 percent higher than the prior encoding techniques. The proposed method is 30.3 percent more energy efficient than the conventional 4LC and this is similar or higher than other energy efficiency improvement methods.

Review on modeling and application of chemical mechanical polishing

Abstract With the development of integrated circuit technology, especially after entering the sub-micron process, the reduction of critical dimensions and the realization of high-density devices, the flatness between integrated circuit material layers is becoming more and more critical. Because conventional mechanical polishing methods inevitably produce scratches of the same size as the device in metal or even dielectric layers, resulting in depth of field and focus problems in lithography. The first planarization technique to achieve application is spin on glass (SOG) technology. However, this technology will not only introduce new material layers, but will also fail to achieve the global flattening required by VLSI and ULSI technologies. Moreover, the process instability and uniformity during spin coating do not meet the high flatness requirements of the wafer surface. Also, while some techniques such as reverse etching and glass reflow can achieve submicron level regional planarization. After the critical dimension reaches 0.35 microns (sub-micron process), the above methods cannot meet the requirements of lithography and interconnect fabrication. In the 1980s, IBM first introduced the chemical mechanical polishing (CMP) technology used to manufacture precision optical instruments into its DRAM manufacturing [1]. With the development of technology nodes and critical dimensions, CMP technology has been widely used in the Front End Of Line (FEOL) and Back End Of Line (BEOL) processes [2]. Since the invention of chemical mechanical polishing, scientists have not stopped studying its internal mechanism. From the earliest Preston Formula (1927) to today’s wafer scale, chip scale, polishing pad contact, polishing pad - abrasive - wafer contact and material removal models, there are five different scale models from macro to the micro [3]. Many research methods, such as contact mechanics, multiphase flow kinetics, chemical reaction kinetics, molecular dynamics, etc., have been applied to explain the principles of chemical mechanical polishing to establish models. This paper mainly introduces and summarizes the different models of chemical mechanical polishing technology. The various application scenarios and advantages and dis-advantages of the model are discussed, and the development of modeling technology is introduced.

System-Level Leakage Power Estimation Model for ASIC Designs

With advances in CMOS- technology and sub-micron process, leakage power dissipation has become a critical design metric. To incorporate more functions, designs are getting complex, thereby increases leakage power dissipation. Low power design objective requires early exploration and estimation. In this paper, we present the power estimation models for ASIC (Application Specific Integrated Circuit) based designs at the C-level of abstraction. The method includes analysis and extraction of the application specific information from the LLVM (Low-Level Virtual Machine) bit-code; which further applies to train the neural network. The trained model is applied in the estimation of the leakage power. Estimation of design power using our models is compared to the implemented measurement, which demonstrates its accuracy. In addition, the proposed methodology is significantly quicker and abolishes the need of synthesis based exploration.

Perimeter Gated Single Photon Avalanche Diodes in Sub-Micron and Deep-Submicron CMOS Processes

A perimeter gated SPAD (PGSPAD), a SPAD with an additional gate terminal, prevents premature perimeter breakdown in standard CMOS SPADs. At the same time, a PGSPAD takes advantage of the benefits of standard CMOS. This includes low cost and high electronics integration capability. In this work, we simulate the effect of the applied voltage at the perimeter gate to develop a consistent electric field distribution at the junction through physical device simulation. Additionally, the effect of the shape of the device on the electric field distribution has been examined using device simulation. Simulations show circular shape devices provide a more uniform electric field distribution at the junction compared to that of rectangular and octagonal devices. We fabricated PGSPAD devices in a sub-micron process (0.5 μm CMOS process and 0.5 μm high voltage CMOS process) and a deep-submicron process (180 nm CMOS process). Experimental results show that the breakdown voltage increases with gate voltage. The breakdown voltage increases by approximately 1.5 V and 2.5 V with increasing applied gate voltage magnitude from 0 V to 6 V for devices fabricated in 0.5 μm and 180 nm standard CMOS process respectively.

Advanced layout techniques for high‐speed analogue circuits in 28 nm HKMG CMOS process

This paper investigates the effect of optimizing the transistor finger width on the performance of high-speed analogue circuits in deep sub-micron processes, demonstrated in a 28nm High-K/Metal Gate (HKMG) CMOS technology process. Silicon proven results demonstrate that the oscillator with a finger width of 440nm gives the best performance based on the Figure of Merit (=142) among the benchmark design examples used.

Leakage Power Reduction by using Sleep Switches in Domino Logic Circuit Design in DSM Technology

Power consumption is hurdle problem face by nanometer CMOS circuit in deep submicron process (DSM) technology. As technology scales down, leakage power significantly increases very rapidly due to high transistor density, reduced voltage and oxide thickness. A new circuit technique based on: “Sleep Switch” is proposed in this paper for reducing the subthreshold and gate oxide leakage currents when circuit is operating in idle and non idle mode in domino circuit design. In this technique a p-type and an n-type leakage controlled sleep transistor are introduced between the pull-up and pull-down network and their gates are controlled by the source of the other. For any combination of input, one of the Sleep transistor will operate near cut off region which increase the resistance path between supply voltage and ground resulting in reduced leakage current. The proposed circuit technique reduces the active power consumption by 14.3% to 44.45% and by 12% to 33% at the low and high die temperature respectively compared to the standard footerless domino logic circuits. During idle mode, 11.64% to 78.39% and 21.2% to 36.19% reduction of leakage current is observed with low and high inputs at 25C and 110C respectively. Similarly, during non-idle mode 0.94% to 99.3% and 1.57% to 98.58% is observed with low and high inputs at 25C to 110C respectively when compared to standard footerless domino logic circuits.

A Thermal Method to Reduce the Polysilicon Resistance for Deep Submicron Integration Process

In the ultra-large-scale integration (ULSI) technologies, polysilicon resistors are usually employed in the integrated circuits as a precise analog resistor element for a variety of applications, such as DAC (digital resistor give the solution of the linearity and Rs concerns to analog converter) in analogue circuits [1-3]. Conventionally the polysilicon resistance can be adjusted by ion implantation and post annealing process [4]. For the self-aligned implantation process, the dosage changes which are always utilized to adjust the resistance are feasible to induce the MOS characteristics changes, especially in the submicron process whose short-channel effects (SCE) are much more sensitive to the dosages [5]. In this work, we propose a new inner anneal process in N2ambient after polysilicon re-oxidation to reduce the polysilicon resistance by changing the polysilicon grain size. The test patterns are manufactured on 300mm-diameter wafer by 65-nm 1-poly 7-metal standard CMOS technology. After polysilicon re-oxidation to form oxide film on polysilicon surface, the wafers are annealed at 800oC, 900oC, 950oC and 1000oC in N2ambient, respectively. Fig. 1 shows the process flow and annealing process steps in the flow. After anneal, the polysilicon grain size is measured by X-ray powder diffraction (XRD). And the electric characteristics for NMOS, PMOS and polysilicon resistance are tested. Fig. 2 shows the poly resistance reduction proportion and poly grain size after anneal at 800oC, 900oC, and 1000oC for 5min, and 950oC for 20min in N2 ambient, respectively. Only after annealing at 950oC or above for 5min, the resistance can be obviously reduced, due to the poly grain size increasing. Fig. 3 shows threshold voltages (Vt) variation proportions of NMOS and PMOS owning gate length of 65nm and width 0.12µm after utilizing annealing process at different temperatures. PMOS is more sensitive to the anneal process than NMOS. But after anneal at 950oC or below, the threshold variation for both NMOS and PMOS is less than 5%, which is acceptable for the integration process manufacturing. A new anneal process at N2 ambient to adjust the polysilicon resistance has been proposed. It has been verified that utilizing anneal process at 950oC or below, the 65nm MOS performances can be maintained almost same as before. Consequently, it is considered that the anneal method can be to be applied to the deep submicron integration process.

Dose-rate sensitivity of deep sub-micro complementary metal oxide semiconductor process

Enhancing low dose rate sensitivity (ELDRS) in bipolar device is a major problem of liner circuit radiation hardness prediction for space application. ELDRS is usually attributed to space-charge effect. A key element is the difference in transport rate between holes and protons in SiO2. Interface-trap formation at high dose rate is reduced due to positive charge buildup in the Si/SiO2 interfacial region (due to the trapping of holes and/or protons) which reduces the flow rates of subsequent holes and protons (relative to the low-dose-rate case) from the bulk of the oxide to the Si/SiO2 interface. Generally speaking, the dose rate of metal oxide semiconductor (MOS) device is time dependent when annealing of radiation-induced charge is taken into account. The degradation of MOS device induced by the low dose rate irradiation is the same as that by high dose rate when annealing of radiation-induced charge is taken into account. However, radiation response of new generation MOS device is dominated by charge buildup in shallow trench isolation (STI) rather than gate oxide as older generation device. Unlike gate oxides, which are routinely grown by thermal oxidation, field oxides are produced using a wide variety of deposition techniques. As a result, they are typically thick (100 nm), soft to ionizing radiation, and electric field is far less than that of gate oxide, which is similar to the passivation layer of bipolar device and may lead to ELDRS. Therefore, dose-rate sensitivities of n-type metal oxide semiconductor field effect transistor (NMOSFET) and static random access memory (SRAM) manufactured by 0.18 m complementary metal oxide semiconductor (CMOS) process are explored experimentally and theoretically in this paper. Radiation-induced leakages in NMOSFET and SRAM are examined each as a function of dose rate. Under the worst-case bias, the degradation of NMOSFET is more severe under the low dose rate irradiation than under the high dose rate irradiation and anneal. Moreover, radiation-induced standby current rising in SRAM is more severe under the low dose rate irradiation than under the high dose rate irradiation even when anneal is not considered. The above experimental results reveal that the dose-rate sensitivity of deep sub-micron CMOS process is not related to time-dependent effects of CMOS devices. Mathematical description of the combination between enhanced low dose-rate sensitivity and timedependent effects as applied to radiation-induced leakage in NMOSFET is developed. It has been numerically found that non time-dependent effect of deep sub-micron CMOS device arises due to the competition between enhanced low dose-rate sensitivity in bottom of STI and time-dependent effect at the top of STI. The high dose rate irradiation is overly conservative for devices used in a low dose rate environment. The test method provides an extended room temperature anneal test to allow leakage-related parameters that exceed postirradiation specifications to return to a specified range.

Impact of Heterogeneous Technology Integration on the Power, Performance, and Quality of a 3D Image Sensor

This work investigates the effect of heterogeneous technology integration on a 3D integrated image sensor. A system level model is discussed that analyzes the correlation between design choices, power, performance, thermal, and noise. As a case study, a 3D image sensor is analyzed considering a photosensor module designed in 180 nm process, and a compression engine implemented in 180, 90, and 45 nm processes. The coupled analysis shows that scaling down the compression engine to deep sub-micron process provides higher throughput for a given system power or reduces power for a target throughout, but die-to-die thermal coupling can modulate quality of the compressed images.

Input–output Rail-to-Rail CMOS CCII for low voltage–low power applications

This paper presents a novel circuit design for input–output Rail-to-Rail CMOS Second Generation Current Conveyor (CCII) for low voltage and low power applications. The designed circuit is structured from a single stage Rail-to-Rail Operational Amplifier (Op-Amp) and a conventional CMOS inverter as a class AB amplifier. Therefore, it provides a high wide range for input signal and high output current driving capability operation. In this paper, a new technique for an automated design script is created to produce a constant trans-conductance (gm) for the Rail-to-Rail Op-Amp using Open Command Environment (OCEAN) script language. The proposed Rail-to-Rail Op-Amp is based on a DC level shifter technique, which is cited at the input stage. This script allows the design problem to be cast as a program. Therefore, it offers an efficient, reliable, and fast way to implement high-performance of analog integrated circuits. Moreover, the physics-based gm/ID characteristic is used that is more suitable for short channel transistors in sub-micron processes. The circuit is simulated in IBM 0.13µ CMOS technology with a single power supply 1.5-V. Virtuoso layout editor tool with caliber tools from Mentor Graphics are used to carry out the layout of the proposed circuit. The chip is fabricated by MOSIS Educational Program (MEP) and is tested to evaluate the performance of the proposed circuits. The measured and simulation results indicate a good agreement.

A 65-nm 1-Gb NOR floating-gate flash memory with less than 50-ns access time

This paper presents a 65-nm 1-Gb NOR-type floating-gate flash memory, in which the cell device and chip circuit are developed and optimized. In order to solve the speed problem of giga-level NOR flash in the deep sub-micron process, the models of long bit-line and word-line are first given, by which the capacitive and resistive loads could be estimated. Based on that, the read path and key modules are optimized to enhance the chip access property and reliability. With the measurement results, the flash memory cell presents good endurance and retention properties, and the macro is operated with 1-µs/byte program speed and less than 50-ns read time under 3.3 V supply.

A Split-Path Sensing Circuit for Spin Torque Transfer MRAM

As process technology scales down, sensing becomes difficult during read operations because the supply voltage, i.e., VDD, decreases and the process variation increases. Thus, a high enough sensing yield cannot be obtained with a conventional sensing circuit in deep submicron process technology. In this brief, a split-path sensing circuit is proposed to achieve a large enough sensing margin by using a variable reference voltage. The proposed sensing circuit is verified using Monte Carlo HSPICE simulation with industry-compatible low-leakage 45-nm model parameters. The proposed circuit has a sensing yield of 99% for 1-Mb memory with a sensing time of 1 ns and a sensing yield of 99% for 32-Mb memory with a sensing time of 3 ns.

Hardware accelerated smart-card software evaluation supported by information leakage and activity sensors

System integration density increased tremendously in recent years, resulting in various problems for designers. First, a variety of dependability issues were a direct consequence from high clock frequencies and system-on-chip complexity, such as thermal, power, and stability challenges. Furthermore, deep sub-micron semiconductor processes were increasingly prone to single-event-upsets and multiple-event-upsets caused by logic degradation and environmental sources. Besides these reliability issues, the intentional introduction of faults into the system by adversaries, is of increasing concern to system developers of smart-cards. Therefore, there is a strong need for hardware-accelerated evaluation techniques during the design phase to identify weaknesses in cryptographic software implementations. To map power and fault models to such FPGA-based evaluation systems, characterization and benchmark approaches are described in literature, using general purpose benchmark software. Unfortunately, such non-specialized software can lead to various evaluation problems. Therefore, this paper proposes an hardware-accelerated methodology for the investigation of software implementations in the security and dependability domains. The applicability of the approach has been shown using a general available system-on-chip implementation.

CMOS sensors in 90 nm fabricated on high resistivity wafers: Design concept and irradiation results

The LePix project aims at improving the radiation hardness and the readout speed of monolithic CMOS sensors through the use of standard CMOS technologies fabricated on high resistivity substrates. In this context, high resistivity means beyond 400Ωcm, which is at least one order of magnitude greater than the typical value (1–10Ωcm) adopted for integrated circuit production. The possibility of employing these lightly doped substrates was offered by one foundry for an otherwise standard 90 nm CMOS process. In the paper, the case for such a development is first discussed. The sensor design is then described, along with the key challenges encountered in fabricating the detecting element in a very deep submicron process. Finally, irradiation results obtained on test matrices are reported.

Gate-leakage compensation scheme for programmable SI-DAC of ΣΔ modulator in deep sub-micron

A gate-leakage compensation scheme is proposed to solve the gate-leakage current issue caused by large-size current-source transistors in multi-bit switched-current (SI) DACs of the continuous-time ΣΔ modulator in deep sub-micron process without extra power consumption. To cover wide current range due to variable coefficients in different modes, the programmable SI-DAC architecture with 2-bit digital controlled unit cells is proposed. Implemented in 65 nm CMOS, the simulated results verify that the proposed scheme solves the gate-leakage issue and the modulator achieves tremendously high performance of 84.5 dB SQNDR and 94.6 dB SFDR with almost 14 and 19 dB improvement in SQNDR and SFDR, respectively.

An Analytical Model of Conversion Gain for Submicron Active Mixers with LO Offsets

The conversion gain of CMOS active mixers is investigated in terms of several kinds of LO offsets. With the effect of output resistance characterized in submicron process, the effective transconductance of driving stage is rigorously derived based on small-signal cascode equivalence. An analytical conversion gain model for the mixer with several kinds of LO offsets is thus presented. Based on Chartered 0.35 µm CMOS technologies, the Spectre-RF simulations agree with the predictions from the proposed model well, where the maximal error is less than 0.28 dB.