Subthreshold Voltage Research Articles

A Simulation Study for Enhancing the Performance of Luminescent Organic Transistor Using Reduced Voltage and Hole Blocking Layer

Abstract Eco-friendly and biodegradable technology forms the basis of organic electronics. A luminescent organic transistor (LOT) is a device created using this technology, which is capable of emission of light and acting as switch functions in a single unit. This research seeks to develop and model a nonplanar contact heterostructure-based LOT by employing the defect density of states (DOS) to accurately simulate the amorphous nature of organic semiconductors. This study evaluates two high-k dielectric materials, hafnium oxide (HfO2) and poly(vinylidene fluoride-trifluoroethylene)P(VDF-TrFe), to achieve low-voltage operation at (-10V). Furthermore, this study investigated the influence of a hole blocking material, 1,3,5-Tris(3-pyridyl-3-phenyl)benzene(TmPyPB), on device performance. Simulations revealed p-channel transistor characteristics with a maximum source-drain current of (-1.6 mA) and an on-off current ratio exceeding 104 for HfO2, compared to (-0.75 mA) and approximately 104 for P(VDF-TrFe). The model also demonstrated exceptional electrical properties, including a peak hole mobility of (1.96 cm2 v-1 s-1), a threshold voltage of (-0.85 V), and a sub-threshold voltage of 492 mV/dec in saturation. The recombination zone exhibited an electron concentration of 18.0 cm-3, a hole concentration of 19.3 cm-3, and a Langevin recombination rate of 24.7 cm-3s-1 near the drain electrode. This model serves as an ideal platform for testing newly developed molecules to enhance the performance of luminescent transistor.

A 1 V supply 10.3 ppm/°C 59 nW subthreshold CMOS voltage reference

—A low temperature coefficient (TC), low power subthreshold CMOS voltage reference (CVR) over a wide temperature range is presented in this paper. The proposed circuit employs the voltage difference between the two inputs of the operational amplifier as the proportional to absolute temperature (PTAT) voltage and the complementary to absolute temperature (CTAT) voltage, which is obtained by the ΔVGS of different-threshold transistors biased in the subthreshold region. The proposed CVR was designed in the 0.18-μm CMOS process with a total area of 0.0049 mm2. It achieves an average temperature coefficient (TC) of 10.3 ppm/°C over a temperature range of −40 °C–120 °C, with a TC of 4.9 ppm/°C at the TT corner. The measured power supply rejection ratio (PSRR) is −65 dB at 10 Hz and −30 dB at 1 MHz, while the power consumption is 59 nW at a supply voltage of 1 V. The average line sensitivity (LS) is 0.16 %/V, and the LS is 0.09 %/V at the TT corner.

A Reinterpretation of the Relationship between Persistent and Resurgent Sodium Currents.

The resurgent sodium current (INaR) activates on membrane repolarization, such as during the downstroke of neuronal action potentials. Due to its unique activation properties, INaR is thought to drive high rates of repetitive neuronal firing. However, INaR is often studied in combination with the persistent or noninactivating portion of sodium currents (INaP). We used dynamic clamp to test how INaR and INaP individually affect repetitive firing in adult cerebellar Purkinje neurons from male and female mice. We learned INaR does not scale repetitive firing rates due to its rapid decay at subthreshold voltages and that subthreshold INaP is critical in regulating neuronal firing rate. Adjustments to the voltage-gated sodium conductance model used in these studies revealed INaP and INaR can be inversely scaled by adjusting occupancy in the slow-inactivated kinetic state. Together with additional dynamic clamp experiments, these data suggest the regulation of sodium channel slow inactivation can fine-tune INaP and Purkinje neuron repetitive firing rates.

A Reinterpretation of the Relationship Between Persistent and Resurgent Sodium Currents.

The resurgent sodium current (INaR) activates on membrane repolarization, such as during the downstroke of neuronal action potentials. Due to its unique activation properties, INaR is thought to drive high rates of repetitive neuronal firing. However, INaR is often studied in combination with the persistent or non-inactivating portion of sodium currents (INaP). We used dynamic clamp to test how INaR and INaP individually affect repetitive firing in adult cerebellar Purkinje neurons from male and female mice. We learned INaR does not scale repetitive firing rates due to its rapid decay at subthreshold voltages, and that subthreshold INaP is critical in regulating neuronal firing rate. Adjustments to the Nav conductance model used in these studies revealed INaP and INaR can be inversely scaled by adjusting occupancy in the slow inactivated kinetic state. Together with additional dynamic clamp experiments, these data suggest the regulation of sodium channel slow inactivation can fine-tune INaP and Purkinje neuron repetitive firing rates.

A 8.83 ppm/°C temperature coefficient, 75 dB PSRR subthreshold CMOS voltage reference with piecewise curvature compensation

A subthreshold CMOS voltage reference (CVR) with low temperature coefficient (TC) over a wide temperature range and low power is proposed in this paper. The proposed CVR utilizes the ΔVGS of different-threshold and same-threshold nMOS pairs to generate complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages, respectively. To compensate for the low-temperature and high-temperature segments of the temperature characteristic curve, the nonlinear compensation currents generated by the exponential-like relationship between the drain current and the gate-source voltage of two MOSFETs work in the subthreshold region is used. Based on a 0.18-μm CMOS process, post-layout simulation results show that the proposed CVR achieves an average output voltage of 263 mV. The power supply ripple rejection (PSRR) is −75 dB at 10 Hz and the line sensitivity (LS) is 0.0069 %/V when the supply voltage varies from 0.8 V to 2.5 V. The average TC is 8.83 ppm/°C for a wide temperature range of −40 °C–120 °C, and the minimum TC is only 3.65 ppm/°C.

A 1.65‐nW 11.14‐ppm/°C self‐biased subthreshold CMOS voltage reference with temperature compensation circuit

SummaryThis paper presents a subthreshold CMOS voltage reference (VR) that utilizes self‐biased circuits. This voltage reference includes temperature compensation circuits to expand its operating temperature range and reduce its temperature coefficient. The proposed CMOS voltage reference is designed using a standard 0.18‐μm CMOS process and has a small area of only 0.005 mm2. Post‐layout simulation results demonstrate that the power consumption of the circuit at room temperature (25°C) is only 1.65 nW at a power supply voltage of 1 V. In this case, the voltage reference output is 316.56 mV, with an average temperature coefficient (TC) of 11.14 ppm/°C in a wide temperature range from −40°C to 140°C. Furthermore, the line sensitivity (LS) of the circuit is 0.024%/V, and the power supply rejection ratio (PSRR) of the circuit is −86.5 dB at 10 Hz. In summary, the subthreshold CMOS voltage reference structure proposed in this paper demonstrates excellent performance characteristics, such as low power consumption, a small area, and high‐temperature stability. These features make it a promising candidate for voltage reference for low‐power applications with significant changes in environmental temperature.

Input Voltage-Level Driven Split-Input Inverter Level Shifter for Nanoscale Applications

A level shifter (LS) appears to be highly efficient and effective in solving voltage contentions between deep sub-threshold and core voltage levels. An input voltage-level driven split-input inverter that can create common unconnected PMOS and NMOS transistors for the input inverter is proposed, which is powered and used at the input stage to achieve maximum conversion efficiency. Layout and simulation results across different corners have demonstrated that the proposed LS is highly useful for cutting-edge nanoscale applications. It can up-convert voltage from 0.2 V to 1.2 V and down-convert from 1.2 V to 0.2 V @ 1 MHz input pulse, with a level-up or level-down mean switching delay of 1.3 ns, and a power of 9.5 nW. Moreover, the LS occupies an area of 8 μm2, which is a reasonably compact size compared to the typical LS designs. Overall, the proposed voltage LS design is an efficient and effective solution that could have an ample range of applications in IoT and biomedical, wireless sensor networks.

A 0.75V 10nm FinField-Effect Transistor Based Hybrid Self Controlled PreCharge Free Content Addressable Memory for Low Standby Power Applications

ABSTRACT The switching speed and driving capability have been enhanced by scaling the transistor size to nanoscale. The limitations in using MOSFET are that the short channel effects such as leakage current, subthreshold voltage, etc. thereby the Complementary Metal Oxide Semiconductor (CMOS) scaling is challenging now.This leads to the emergence of multi-gate devices, such as Fin Field Effect Transistor (FinFET) and Double Gate FinFET (DG-FinFET), which reduces the short channel effect. Now, a days memory plays a vital role in Integrated Circuits (IC), so the size of it must be scaled down to reduce the overall leakage andinstead of CMOS an advanced MOSFET such as FinFET can be used to avoid SCE. The area of the memory Static Random Access Memory (SRAM) is reduced by eliminating the two-load transistor. The novel 4T SRAM is designed at 10 nm 0.75 v FinFET Technology and compared with 14 nm Technology that is inbuilt into content addressable memory (CAM) to reduce the power consumption of CAM. The results show that the proposed design improves on a voltage basis and the complexity of the circuit is reduced by about 23% in terms of transistor count compared with the other conventional techniques. The 10 nm FinFET Hybrid Self Controlled - PreCharge Free (HSCPF) CAM design is best-suitable for low-power applications.

An inverted T-shaped vertical tunneling InN/InxGa1-xN heterojunction TFET with high current ratio

An inverted T-shaped vertical InN/InGaN tunneling field effect transistor (TFET) with polarization-induced doping and high current ratio is proposed and investigated. An optimal structure of the proposed device is given by comparing on-state current, subthreshold voltage, and on-state/off-state current ratio. The polarization effect in III-N material induces electrons and holes in the source and drain regions, and non-physical doping can avoid random dopant fluctuations (RDFs) and high thermal budget. The InN/InGaN heterojunction TFET shows significant improvement over the homojunction TFET. The inverted T-shaped structure involves line and point tunneling simultaneously, so the proposed device can achieve higher on-state current than the conventional device. In addition, the proposed device shows the suppression of ambipolar current. The simulations reveal that the ION/IOFF of the proposed structure is about 6.91 × 1012. These results indicate that the line tunneling structure is still available in the polarization-induced InN/InGaN TFET.

Ultrahigh-gain organic transistors based on van der Waals metal-barrier interlayer-semiconductor junction.

Intrinsic gain is a vital figure of merit in transistors, closely related to signal amplification, operation voltage, power consumption, and circuit simplification. However, organic thin-film transistors (OTFTs) targeted at high gain have suffered from challenges such as narrow subthreshold operating voltage, low-quality interface, and uncontrollable barrier. Here, we report a van der Waals metal-barrier interlayer-semiconductor junction-based OTFT, which shows ultrahigh performance including ultrahigh gain of ~104, low saturation voltage, negligible hysteresis, and good stability. The high-quality van der Waals-contacted junctions are mainly attributed to patterning EGaIn liquid metal electrodes by low-energy microfluidic processes. The wide-bandgap semiconductor Ga2O3 as barrier interlayer is achieved by in situ surface oxidation of EGaIn electrodes, allowing for an adjustable barrier height and expected thermionic emission properties. The organic inverters with a high gain of 5130 and a simplified current stabilizer are further demonstrated, paving a way for high-gain and low-power organic electronics.

M-type potassium currents differentially affect activation of motoneuron subtypes and tune recruitment gain.

The size principle is a key mechanism governing the orderly recruitment of motor units and is believed to be dependent on passive properties of the constituent motoneurons. However, motoneurons are endowed with voltage-sensitive ion channels that create non-linearities in their input-output functions. Here we describe a role for the M-type potassium current, conducted by KCNQ channels, in the control of motoneuron recruitment in mice. Motoneurons were studied with whole-cell patch clamp electrophysiology in transverse spinal slices and identified based on delayed (fast) and immediate (slow) onsets of repetitive firing. M-currents were larger in delayed compared to immediate firing motoneurons, which was not reflected by variations in the presence of Kv7.2 or Kv7.3 subunits. Instead, a more depolarized spike threshold in delayed-firing motoneurons afforded a greater proportion of the total M-current to become activated within the subthreshold voltage range, which translated to a greater influence on their recruitment with little influence on their firing rates. Pharmacological activation of M-currents also influenced motoneuron recruitment at the population level, producing a rightward shift in the recruitment curve of monosynaptic reflexes within isolated mouse spinal cords. These results demonstrate a prominent role for M-type potassium currents in regulating the function of motor units, which occurs primarily through the differential control of motoneuron subtype recruitment. More generally, these findings highlight the importance of active properties mediated by voltage-sensitive ion channels in the differential control of motoneuron recruitment, which is a key mechanism for the gradation of muscle force. KEY POINTS: M-currents exert an inhibitory influence on spinal motor output. This inhibitory influence is exerted by controlling the recruitment, but not the firing rate, of high-threshold fast-like motoneurons, with limited influence on low-threshold slow-like motoneurons. Preferential control of fast motoneurons may be linked to a larger M-current that is activated within the subthreshold voltage range compared to slow motoneurons. Larger M-currents in fast compared to slow motoneurons are not accounted for by differences in Kv7.2 or Kv7.3 channel composition. The orderly recruitment of motoneuron subtypes is shaped by differences in the contribution of voltage-gated ion channels, including KCNQ channels. KCNQ channels may provide a target to dynamically modulate the recruitment gain across the motor pool and readily adjust movement vigour.

A MOSFET subdivision, MOSFET-only subthreshold voltage and current reference for LDO applications

This paper proposes a MOSFET-only voltage and current reference circuit, which can simultaneously provide a 2 V reference voltage and 300 nA reference current. This design is mainly used in a low-power Low-Dropout Regulator (LDO) project, after simulation verification, which works well in LDO applications. The circuit is performed by SMIC.18 CMOS technology and simulation with the Cadence platform, with different threshold voltage MOSFET circuit design. The whole circuit works in the subthreshold area, and the overall circuit consists of the start-up circuit, the current reference circuit, the voltage reference circuit, the MOSFET subdivision circuit, and the current mirror output circuit. The circuit has the characteristics of high precision and low power consumption, with a layout size of only 0.015 mm2. Under a temperature range of -30 to 70 °C and a power voltage of 3.3 V, the simulation and post-simulation temperature coefficients (TC) of the circuit are 5.4 ppm/°C and 19.4 ppm/°C, respectively. The post-simulation output reference voltage at room temperature is 2.0008 V, and the working power voltage within the circuit error range is 3.2 V to 3.4 V. Excluding the current mirror output circuit part of the Current-Quiescent (IQ) being 530 nA, the power consumption is 1.75 μW when the supply voltage is 3.3 V, and the design goal is reached.

An Aqueous Process for Preparing Flexible Transparent Electrodes Using Non-Oxidized Graphene/Single-Walled Carbon Nanotube Hybrid Solution.

In this study, we prepared flexible and transparent hybrid electrodes based on an aqueous solution of non-oxidized graphene and single-walled carbon nanotubes. We used a simple halogen intercalation method to obtain high-quality graphene flakes without a redox process and prepared hybrid films using aqueous solutions of graphene, single-walled carbon nanotubes, and sodium dodecyl sulfate surfactant. The hybrid films showed excellent electrode properties, such as an optical transmittance of ≥90%, a sheet resistance of ~3.5 kΩ/sq., a flexibility of up to ε = 3.6% ((R) = 1.4 mm), and a high mechanical stability, even after 103 bending cycles at ε = 2.0% ((R) = 2.5 mm). Using the hybrid electrodes, thin-film transistors (TFTs) were fabricated, which exhibited an electron mobility of ~6.7 cm2 V-1 s-1, a current on-off ratio of ~1.04 × 107, and a subthreshold voltage of ~0.122 V/decade. These electrical properties are comparable with those of TFTs fabricated using Al electrodes. This suggests the possibility of customizing flexible transparent electrodes within a carbon nanomaterial system.

Temporal dynamics of Na/K pump mediated memory traces: insights from conductance-based models of Drosophila neurons.

Sodium potassium ATPases (Na/K pumps) mediate long-lasting, dynamic cellular memories that can last tens of seconds. The mechanisms controlling the dynamics of this type of cellular memory are not well understood and can be counterintuitive. Here, we use computational modeling to examine how Na/K pumps and the ion concentration dynamics they influence shape cellular excitability. In a Drosophila larval motor neuron model, we incorporate a Na/K pump, a dynamic intracellular Na+ concentration, and a dynamic Na+ reversal potential. We probe neuronal excitability with a variety of stimuli, including step currents, ramp currents, and zap currents, then monitor the sub- and suprathreshold voltage responses on a range of time scales. We find that the interactions of a Na+-dependent pump current with a dynamic Na+ concentration and reversal potential endow the neuron with rich response properties that are absent when the role of the pump is reduced to the maintenance of constant ion concentration gradients. In particular, these dynamic pump-Na+ interactions contribute to spike rate adaptation and result in long-lasting excitability changes after spiking and even after sub-threshold voltage fluctuations on multiple time scales. We further show that modulation of pump properties can profoundly alter a neuron's spontaneous activity and response to stimuli by providing a mechanism for bursting oscillations. Our work has implications for experimental studies and computational modeling of the role of Na/K pumps in neuronal activity, information processing in neural circuits, and the neural control of animal behavior.

A sequential strong PUF architecture based on reconfigurable neural networks (RNNs) against state-of-the-art modeling attacks

Modeling attacks such as machine learning attacks are pretty efficient in breaking hardware security primitives like silicon strong physical unclonable functions (PUFs). As compared to regular strong PUFs such as arbiter PUFs and lightweight (LW)-PUFs, subthreshold current array (SCA)-PUFs exhibit a better resilience against modeling attacks since they utilize the non-linear relationship between the subthreshold current and gate voltage of transistors to obfuscate the corresponding relationship between input challenge and output response. Unfortunately, the degree of non-linearity (DoNL) within SCA-PUFs is still not sufficiently high to resist against state-of-the-art modeling attacks. Therefore, to further enhance DoNL for resisting against modeling attacks, a new strong PUF architecture is proposed in this paper by embedding reconfigurable neural networks (RNNs) into SCA-PUFs. Mathematical foundations are established for finding appropriate RNNs that are able to maximize the DoNL of an SCA-PUF. As shown in the result, when state-of-the-art modeling attacks like Lagrange multiplier attacks (LMAs) are selected, the robustness of the proposed RNN-embedded SCA-PUF is enhanced over 20 times with less than 18.5% power and area overhead as compared to a regular SCA-PUF.

Transient photocurrents in a subthreshold evidence accumulator accelerate perceptual decisions

Perceptual decisions are complete when a continuously updated score of sensory evidence reaches a threshold. In Drosophila, αβ core Kenyon cells (αβc KCs) of the mushroom bodies integrate odor-evoked synaptic inputs to spike threshold at rates that parallel the speed of olfactory choices. Here we perform a causal test of the idea that the biophysical process of synaptic integration underlies the psychophysical process of bounded evidence accumulation in this system. Injections of single brief, EPSP-like depolarizations into the dendrites of αβc KCs during odor discrimination, using closed-loop control of a targeted opsin, accelerate decision times at a marginal cost of accuracy. Model comparisons favor a mechanism of temporal integration over extrema detection and suggest that the optogenetically evoked quanta are added to a growing total of sensory evidence, effectively lowering the decision bound. The subthreshold voltage dynamics of αβc KCs thus form an accumulator memory for sequential samples of information.

A high‐efficiency power management unit with wide dynamic range for RF energy harvesting system

AbstractA high‐efficiency power management unit (PMU) with wide dynamic range for radio frequency (RF) energy harvesting system is proposed in this paper. A digital zero current switching (ZCS) and a digital maximum power point tracking (MPPT) circuits are adopted. A sub‐threshold current reference circuit and a subthreshold voltage detection circuit are proposed to reduce the power consumption of always‐on control circuits and improve the conversion efficiency at low input power. A dual‐oscillator is designed to extend the frequency range and widen the input power range with optimized power consumption under low‐end band and high‐end band, respectively. Switch size and on‐time are adjusted according to the input power, which optimizes the conversion efficiency in a wide power range. Proposed PMU is implemented in a standard 180 nm CMOS process. The post‐layout simulation results show that proposed PMU can achieve cold‐start at the input voltage of 280 mV, the power consumption to maintain the PMU is only 9.6 nW. The input power range of the PMU is 11 nW–677 μW. When the input power is 50 nW, a power conversion efficiency (PCE) of 65% is achieved, and the peak PCE can reach 93% at 23.5 μW.

Highly Sensitive Hybrid Oxide Phototransistors with Photoresponsive Zeolitic‐Imidazolate‐Frameworks for Real‐Time Light Detection

AbstractConventional oxide‐based thin‐film phototransistors (Ph‐TRs) with a hybrid structure with additional photoabsorbers show limitations in real‐time on/off operations without additional input bias. Here, hybrid InGaZnO (IGZO) Ph‐TRs utilizing zeolitic‐imidazolate‐framework‐67 (ZIF‐67), an electrically insulating material with a unique metal‐to‐metal charge transfer (MMCT) pathway enabling charge migration, are presented. A wide photodetection range and fast response/recovery speed without additional gate bias are achieved. In particular, ZIF‐67 used as a photoabsorber exhibits absorption of visible light over a wide range of wavelengths. Photoexcited electrons migrate through the MMCT pathway between Co ions and migrate to the IGZO conduction band, causing a significant change in the photocurrent (Iph) of the hybrid ZIF‐67/IGZO Ph‐TR. In the dark, ZIF‐67 immediately returns to the insulating state, resulting in a fast rise/fall time under dynamic photo‐stimulus. In addition, it exhibits repeatable photo‐sensing performance without persistent photocurrent behavior under pulsed light‐on/off cycles. A high photosensitivity of 108 for red light (592 nm, 0.1 mW cm–2) is obtained as it suppresses the dark current and amplifies photocurrent generation in the subthreshold gate voltage region. This combination of fast response time, high photosensitivity, and high stability is promising for ideal Ph‐TRs, enabling real‐time detection even for high‐frequency operations.

A 21.4 pW Subthreshold Voltage Reference with 0.020 %/V Line Sensitivity Using DIBL Compensation.

This paper presents an ultra-low-power voltage reference designed in 180 nm CMOS technology. To achieve near-zero line sensitivity, a two-transistor (2-T) voltage reference is biased with a current source to cancel the drain-induced barrier-lowering (DIBL) effect of the 2-T core, thus improving the line sensitivity. This compensation circuit achieves a Monte-Carlo-simulated line sensitivity of 0.035 %/V in a supply range of 0.6 to 1.8 V, while generating a reference voltage of 307.8 mV, with 21.4 pW power consumption. The simulated power supply rejection ratio (PSRR) is -54 dB at 100 Hz. It also achieves a temperature coefficient of 24.8 ppm/°C in a temperature range of -20 to 80 °C, with a projected area of 0.003 mm2.

Ultra-Low-Power Low-Input-Voltage Charge Pump for Micro-Energy Harvesting Applications

A subthreshold input voltage charge pump based on the well-known cross-coupled voltage doubler and using boosted gate voltages for the transfer switches is presented. A level shifter and some inverters, including a novel inverter architecture proposed in this work and referred to as negative low-state voltage inverter, are used to generate the clock signals for the switching transistors with the purpose of significantly improving their drive capability. A complete analysis of the proposed charge pump is provided to highlight the advantages of the implemented structure, revealing the power efficiency improvement when the input voltage is below the threshold voltage of the transistors. An extensive experimental characterization of silicon prototypes in 180 nm CMOS technology was carried out, showing that the proposed scheme is able to pump charge from an input voltage as low as 110 mV. The experimental peak efficiency remains above 70% for input voltages between 180 mV and 400 mV and input power levels from 45 nW to 25 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> , which are appropriate for different miniaturized transducers implementable on chip.