Subthreshold Region Research Articles

Long‐Channel Effects in Randomly Oriented Carbon Nanotube Thin Film Transistors

AbstractCarbon nanotube (CNT) thin film transistors (TFTs) have demonstrated great potential for application in highly sensitive biosensors and large‐area electronics. However, research on the electrical behavior of long‐channel CNT TFTs is lacking; thus, the purposeful improvement in the performance of biosensors or circuits is difficult. In this study, the electrical transport characteristics of ionic‐liquid‐gate CNT TFTs with channel lengths (Lch) ranging from 10 to 400 µm are investigated. The CNT TFTs present classical drift‐diffusion transport at on‐state with a carrier mobility of around 27 cm2 V−1 s−1. In the subthreshold region of the CNT TFTs, an abnormal Lch‐dependent subthreshold swing (SS) relationship, named as the long‐channel effect (LCE)is observed, where SS worsens with increasing Lch. The existence of the junctions between the CNTs results in an unconventional density of states for carriers and a large series resistance for sharing the gate voltage; this dominates the abnormal scaling behavior in the subthreshold region by degrading the electrostatic integrity. The discovery of the abnormal LCE can aid in the construction of device models and purposefully improve the performance of CNT TFTs for biosensors and other large‐scale electronic applications.

Modeling and Analyzing of CMOS Cross-Coupled Differential-Drive Rectifier for Ultra-Low-Power Ambient RF Energy Harvesting

This paper models and analyzes the Complementary Metal Oxide Semiconductor (CMOS) cross-coupled differential-drive (CCDD) rectifier for Ultra-Low-Power ambient radio-frequency energy harvesters (RFEHs) working in the subthreshold region. In this paper, two closed-form equations of CCDD rectifier output voltage and input resistance in the subthreshold region were derived based on BSIM4 models of NMOS and PMOS. The model give insight to specify circuit parameters according to different inputs, transistor sizes, threshold voltages, numbers of stages, load conditions and compensation voltages, which can be used to optimize the rectifier circuit. There is a good agreement between the simulation results and these models, and these models have a maximum deviation of 10% in comparison with the simulation results in the subthreshold region. The measurement results of a single-stage CCDD rectifier reported in a previous paper were adopted to verify the model. The output voltage and input resistance predicted by these models provide excellent consistency with corresponding measurement results. The model can be employed to optimize the CCDD rectifier without expensive calculation in the design stage.

Design of Voltage–Current Reference Source in CMOS Technology

A design methodology for a resistorless low-power two-in-one voltage and current reference source working in subthreshold and moderate regions is described. The presented novel universal reference voltage–current source was implemented in ten different designs for seven different CMOS technologies. Six versions of these designs were silicon-proven using four different CMOS technologies. The example of implementation in 130 nm technology provides a reference current of 5 µA and reference voltage of 800 mV at supply voltages ranging from 0.9 V to 2.0 V with a total current consumption of 15 µA. The proposed circuit occupies a 1200 µm2 chip area and achieves 280 and 118 ppm/°C for all process corners and temperature variation from −40 °C to 125 °C. The power supply rejection ratio of output IREF without any filtering capacitor at 100 Hz and 10 MHz is 128 dB and 100 dB, respectively. The equivalent output current noise in the bandwidth from 1 Hz to 10 MHz reaches 9.1 nARMS.

0.5 V, Low-Power Bulk-Driven Current Differencing Transconductance Amplifier

This paper presents a novel low-power low-voltage current differencing transconductance amplifier (CDTA). To achieve a low-voltage low-power CDTA, the BD-MOST (bulk-driven MOS transistor) technique operating in a subthreshold region is used. The proposed CDTA is designed in 0.18 µm CMOS technology, can operate with a supply voltage of 0.5 V, and consumes 1.05 μW of power. The proposed CDTA is used to realize a current-mode universal filter. The filter can realize five standard transfer functions of low-pass, band-pass, high-pass and band-stop, and all-pass from the same circuit. Neither component-matching conditions nor input signals of the inverse type are required to realize these filter functions. The current-mode filter offers low-input and high-output impedance and uses grounded capacitors. The natural frequency and quality factor of the filters can be orthogonally controlled. The proposed CDTA and its applications are simulated using SPICE to confirm the feasibility and functionality of the new circuits.

A simple picowatt 7.6 ppm/°C, 0.029 %/V line sensitivity fully-CMOS voltage reference with DIBL cancelation

In this paper, a 4-transistor sub-one-volt voltage reference with picowatt power consumption is presented. To achieve ultra-low power consumption and low-voltage operation, all transistors are designed to operate in subthreshold region. By proper design of the circuit, DIBL effect is also compensated to enhance temperature coefficient of the circuit and line sensitivity. The proposed circuit consists of only four different transistors (i.e. thick oxide, native VTH, medium VTH) in a self-biased scheme such that eliminates the need for any start-up circuit. A prototype of the proposed circuit that generates a 341-mV voltage reference is designed and simulated in a standard 0.18-µm CMOS technology. The proposed reference circuit exhibits an average temperature coefficient of 7.6 ppm/°C across all process corners while the total power consumption is as low as 249 picowatt. The average line sensitivity of the circuit is 0.029 %/V within a wide supply range of 0.6 to 3.3 V. Ultra-low power consumption and line sensitivity, and excellent thermal stability render it ideal for integration into RFID and IoT applications.

An analytical I-V model of SiC double-gate junctionless MOSFETs

Silicon carbide(SiC) double gate junctionless metal oxide semiconductor field-effect transistors(DG JL MOSFETs) have attracted significant attention due to their ideal high temperature characteristics and radiation resistance. Therefore, it is meaningful to exploit an I-V model for SiC DG JL MOSFETs. In this article, we make a linear approximation to describe the relationship between the surface mobile charge density and the surface electron concentration of the device. Based on this approximation and using the one-dimensional Poisson’s equation, we solve for the potential distribution of a SiC DG JL MOSFET in the subthreshold region. From this solution, we derived a functional relationship between the surface mobile charge density in the channel and the channel quasi-Fermi potential. Then we successfully developed a unified I-V model for the SiC DG JL MOSFETs. Based on the drain to source current calculation formula, the calculation expressions for the device’s transconductance and output conductance are derived. By comparing our model with the results from the two-dimensional numerical simulation software Silvaco Atlas, our model’s calculations closely match the two-dimensional numerical simulation results from the subthreshold region to the accumulation region. This model has reference significance for SiC DG JL MOSFETs in the high temperature electronic circuit application field.

Characterization of bulk trap density using fully I–V-based optoelectronic differential ideality factor in multi-layer MoS2 FETs

Abstract Molybdenum disulfide (MoS2) has excellent optoelectronic properties, chemical stability, and a two-dimensional (2D) structure, making MoS2 a very versatile field-effect device material. Herein, we characterize MoS2 and utilize a photo-responsive I–V technique for extracting the energy distribution of the bulk traps in multi-layer MoS2 field effect transistors (FET). This method uses the differential ideality factor in both dark and light conditions. The differential ideality factor enables the efficient quantitative extraction of the device trap density by considering the nonlinear characteristics of the subthreshold region (V ON < V GS < V T). To accurately differentiate between the sub-bandgap traps and the interface traps near the conduction band, near-infrared light (λ= 1530 nm) optical illumination was used for the light state characterization. The bulk trap densities under dark state and light state conditions were derived for multi-layer (7-layer and 9-layer) MoS2 FET channels, and the influence of light illumination and overall multi-layer thickness on the bulk trap density was confirmed. The accurate extraction of the trap density enables the design of MoS2 FETs with long-term stability and high optoelectronic performance.

Effect of background noise characteristics on early warning indicators of thermoacoustic instability

In this work, we investigate the effects of background noise characteristics — specifically noise color (or correlation time) and intensity — arising from velocity-coupled and additive noise sources, on the early warning indicators (EWIs) of thermoacoustic instability. We employ a nonlinear reduced-order combustion dynamics model for our investigation. In the absence of noise, the nonlinear model undergoes a subcritical Hopf bifurcation, and our focus lies within the linearly stable region of the system (subthreshold region). The studied class of EWIs encompasses those derived from time series (variance), spectral analysis (coherence factor), Hurst exponent, and nonlinear methods (permutation entropy). We find that when the background noise is purely multiplicative, the trends in EWIs are primarily influenced by noise characteristics rather than the control parameter. Further, the EWIs cannot be estimated at low noise levels for large correlation times. In case of purely additive noise driven system, the coherence factor and variance are reliable EWIs across all range of investigated noise characteristics. The Hurst exponent can serve as effective EWI when the system features large noise correlation times, while permutation entropy is effective only when the system features small noise correlation time, i.e., where white noise assumption is acceptable. When the background noise includes contributions from both multiplicative and additive sources, coherence factor and variance emerges as the most reliable EWIs. These results provide insights for selecting appropriate EWIs to be employed in practical systems, considering potential variations in noise characteristics with simultaneous changes in combustor operating conditions.Novelty and significanceThis study conclusively shows that background noise (multiplicative and additive) characteristics – noise correlation time (color) and intensity – can significantly change the trends in early warning indicators (EWIs) for predicting the impending thermoacoustic oscillations. In gas turbine combustors, where thermoacoustic instability poses a critical challenge, inherent noise dynamics undergo variations with changing operating conditions and combustor designs. The development of effective EWIs to foresee the onset of thermoacoustic instability is crucial for preventing potential damage and ensuring the reliable operation of combustion systems. Previous works on stochastic dynamics of combustors simplify noise with the additive white noise assumption. Thus, our results demonstrated on a nonlinear combustion dynamics model advance the state-of-the-art with respect to the early prediction and control of thermoacoustic instability. The results provide valuable insights for selecting appropriate EWIs for engine monitoring in the absence of information on noise properties and their variation with operating conditions. This practical information is of direct relevance and interest to any gas turbine manufacturer/user.

A 1 V supply 10.3 ppm/°C 59 nW subthreshold CMOS voltage reference

—A low temperature coefficient (TC), low power subthreshold CMOS voltage reference (CVR) over a wide temperature range is presented in this paper. The proposed circuit employs the voltage difference between the two inputs of the operational amplifier as the proportional to absolute temperature (PTAT) voltage and the complementary to absolute temperature (CTAT) voltage, which is obtained by the ΔVGS of different-threshold transistors biased in the subthreshold region. The proposed CVR was designed in the 0.18-μm CMOS process with a total area of 0.0049 mm2. It achieves an average temperature coefficient (TC) of 10.3 ppm/°C over a temperature range of −40 °C–120 °C, with a TC of 4.9 ppm/°C at the TT corner. The measured power supply rejection ratio (PSRR) is −65 dB at 10 Hz and −30 dB at 1 MHz, while the power consumption is 59 nW at a supply voltage of 1 V. The average line sensitivity (LS) is 0.16 %/V, and the LS is 0.09 %/V at the TT corner.

A 0.5 V, 32 nW Compact Inverter-Based All-Filtering Response Modes Gm-C Filter for Bio-Signal Processing

A low-power, low-voltage universal multi-mode Gm-C filter using a 180 nm TSMC technology node is presented in this paper. The proposed filter employs only three transconductance operational amplifiers (OTAs) operating in the sub-threshold region with a supply voltage of 0.5 V, resulting in a power consumption of 32 nW. Moreover, without additional active elements, the proposed circuit can operate various functional modes, such as voltage, current, transconductance, and trans-resistance. The filter’s frequency, centered at 462 Hz, and a compact and low-power solution showing only 93.5 µVrms input-referred noise make the proposed filter highly suitable for bio-signal processing.

Ultra-low-power super class-AB adaptive biasing operational transconductance amplifier with enhanced gain for biomedical applications

The operational transconductance amplifier (OTA) proposed in this article is a bulk-driven (BD), single-stage, super-class-AB, adaptive biasing, functioning in the subthreshold region (ST) with an enormously low power supply of ± 0.25 V, providing high-gain. The input core of the OTA circuit is composed of adaptively biased BD differential input pairs based on flipped voltage follower (FVF), which drive in class-AB mode with a partial positive feedback (PPF) approach. The circuit additionally employs FVF and self-cascode (SC)-based low-power current mirror loads at its output to obtain significantly high gain and unity gain frequency. In addition, using adaptive loads based on source-degenerated metal oxide semiconductor (MOS) resistors raises dynamic current more efficiently, consequently improving the slew rate and unity gain frequency (UGF) without drawing additional power. Employing the cadence spectre tool and the UMC 0.18 μm complementary metal oxide semiconductor (CMOS) process technology, the designed OTA has been simulated. The simulation outcomes substantiate that the amplifier provides high open loop DC gain of 75 dB, 18.75 kHz UGF with a phase margin of 63.93º, and input-referred noise (IRN) of 0.734 µV/Hz0.5 at 1 kHz frequency. The proposed OTA consumes just 60.15 nW of power. The performance results confirmed that the proposed OTA circuit is appropriate in biomedical applications.

A Comprehensive Review of Power Consumption in Digital Logic Circuits at Ultra-Low Subthreshold CMOS Levels

In the anticipated spectrum, a lot of work has gone into managing the trade-offs between power, location, and efficiency in the moderate efficiency, moderate power region. However, research into the extremities of this spectrum remains restricted. In particular, there hasn't been enough research done on the extremes of extraordinarily low power consumption with appropriate efficiency and extraordinary efficiency with energy that is within realistic bounds. In this work, very low subthreshold power levels are used to study the power consumption characteristics of digital logic circuits in static Complementary Metal-Oxide-Semiconductor (CMOS) devices. The study shows that operating transistors below their threshold voltage might result in significant energy savings. This research emphasises the significance of subthreshold design strategies for contemporary electronic circuits that aspire for low-power operation without sacrificing efficiency. The results highlight the potential for significant progress in energy-efficient circuit design and highlight the delicate balance between preserving performance and cutting power usage. As a result, this research adds to our understanding of low-power electronics and provides information that may lead to the development of future technologies that are more efficient and sustainable. Keywords— Power consumption analysis, Digital logic circuits, Ultra-low power, Subthreshold operation, Static CMOS gates

A Review on FPGA-based Architectures for Noise Removal of Digital Images using High-Level Design

Image corruption during the acquisition and transmission operations may be caused by a variety of disturbances. Scientists are still having trouble getting rid of the noise in the original picture. picture denoising is a technique used to improve a picture's visual quality and extract small details from a damaged image. Improving an image to make it crisper than it was originally is the aim of image restoration. The field of image processing is vast. This paper presents the results of some significant work in the subject of image denoising. It looks into image denoising using some of the most recent methods, such as SEPD (Simple Edge Preserved De-noising) and RSEPD (Reduced Simple Edge Preserved De- noising).Image corruption during the acquisition and transmission operations may be caused by a variety of disturbances. Scientists are still having trouble getting rid of the noise in the original picture. picture denoising is a technique used to improve a picture's visual quality and extract small details from a damaged image. Improving an image to make it crisper than it was originally is the aim of image restoration. The field of image processing is vast. This paper presents the results of some significant work in the subject of image denoising. It looks into image denoising using some of the most recent methods, such as SEPD (Simple Edge Preserved De-noising) and RSEPD (Reduced Simple Edge Preserved De- noising). Keywords— Power consumption analysis, Digital logic circuits, Ultra-low power, Subthreshold operation, Static CMOS gates

Off-Current Analysis with Temperature-Dependent Subthreshold Conduction in SiTe Based Amorphous Chalcogenides for Ovonic Threshold Switching Selector Application

Off-Current Analysis with Temperature-Dependent Subthreshold Conduction in SiTe Based Amorphous Chalcogenides for Ovonic Threshold Switching Selector Application

All-2D-Materials Subthreshold-Free Field-Effect Transistor with Near-Ideal Switching Slope.

The Boltzmann Tyranny, set by thermionic statistics, dictates the lower limit of switching slope (SS) of a MOSFET to be 60 mV/dec, the fundamental barrier for low-dissipative electronics. The large SS leads to nonscalable voltage, significant leakage, and power consumption, particularly at short channels, making transistor scaling an intimidating challenge. In recent decades, an array of steep-slope transistors has been proposed; none is close to an ideal switch with ultimately abrupt switching (SS ∼ 0 mV/dec) between the binary logic states. We demonstrated an all-2D-materials van-der-Waals-heterostructure (vdW)-based FET that exhibits ultrasteep switching (0.33 mV/dec), a large on/off current ratio (∼107), and an ultralow off current (∼0.1 pA). The "Subthreshold-Free" operation achieved by the collective behavior of functional materials enables FET switching directly from the OFF-state to the ON-state with entirely eliminated subthreshold region, behaving as the ideal logic switch. Two-inch wafer-scale device fabrication is demonstrated. Boosted by device innovation and emerging materials, the research presents an advancement in achieving the "beyond-Boltzmann" transistors, overcoming one of the CMOS electronics' most infamous technology barriers that have plagued the research community for decades.

Characteristics of Carbon Nanotube Cold Cathode Triode Electron Gun Driven by MOSFET Working at Subthreshold Region.

The carbon nanotube cold cathode has important applications in the X-ray source, microwave tube, neutralizer, etc. In this study, the characteristics of carbon nanotube (CNT) electron gun in series with metal-oxide-semiconductor field-effect transistor (MOSFET) were studied. CNTs were prepared on a stainless steel substrate by chemical vapor deposition and assembled with a mesh gate to form an electron gun. The anode current of the electron gun can be accurately regulated by precisely controlling the MOSFET gate voltage in the subthreshold region from 1 to 40 µA. The current stability measurements show the cathode current fluctuation was 0.87% under 10 h continuous operation, and the corresponding anode current fluctuation was 2.3%. The result has demonstrated that the MOSFET can be applied for the precise control of the CNT electron gun and greatly improve current stability.

Effect of colored noise on precursors of thermoacoustic instability in model gas turbine combustors

In this work, we numerically investigate the dynamics of a prototypical thermoacoustic system, the generalized Van der Pol oscillator, in the presence of additive noise of varying color (correlation time) and intensity while the system undergoes supercritical and subcritical Hopf bifurcation. We specifically investigate the influence of noise color on trends in the coherence factor and the Hurst exponent in the subthreshold region to assess their reliability as instability precursors. The Hurst exponent is found reliable only for correlation times much larger than the time scale of the instability while the coherence factor is found to be reliable for the entire range of noise color investigated. These inferences are found to hold for both supercritical and subcritical bifurcation cases.

Subthreshold read operations in 3D PCM: 1S1R device modeling and memory array analysis

3-D phase change memory (PCM) is one of the most promising next-generation nonvolatile memory, and the subthreshold sensing strategy can effectively improve its limited endurance. In this study, we propose a one-selector-one-resistor (1S1R) model with Monte Carlo (MC) function and provide array configurations for the worst case and the maximum bit line voltage (VBL-max), respectively. Based on these, the read window margin (RWM) is evaluated with various array sizes, OTS threshold voltage variations (σvar), and bias voltages (VBias). Our results reveal that the RWM increases as the VBL approaches the VBL-max. Larger arrays lead to an increased leakage current difference, while larger σvar values result in decreased cell current difference and VBL-max. The decrease in VBL-max further deteriorates the RWM. Additionally, we analyze the optimal VBias for 2-deck arrays achieves a 7% reduction in leakage energy consumption and a 22.6% increase in RWM compared to the V/2 bias. The optimal VBias depends on OTS devices and array sizes.

Simulation based analysis of HK-Ge-Step-FinFET and its usage as inverter & SRAM

This paper deals with comparative simulation of High-k dielectrics -Germanium Step FinFET (HK-Ge-Step-FinFET) device with reference Step FinFET. For the first time we have investigated the impact of various dimensional parameters like oxide thickness tox, gate length Lg, drain bias voltage Vds on the performance of Proposed and Reference FinFET devices. These FinFET structures have been designed and simulated in Sentaurus TCAD and Cadence Virtuoso. The electrical parameters such as current ratio ION/IOFF, Sub-threshold Swing SS , Drain Induced Barrier Lowering (DIBL), threshold voltage Vth, gate capacitance, intrinsic delay and transconductance are extracted at 10 nm gate length. It is noticed that there is a significant improvement of 28 times and 23 times in ION for proposed device over reference FINFET at Vds = 1 V and Vds = 0.5 V respectively, improvement in ION/IOFF ratio from 8.05 × 108 to 6.65 × 1010, SS of 63.21 mV/decade to 61.5 mV/decade and excellent threshold voltage of 0.18 V in proposed FinFET. The characteristics of the proposed SRAM cell including, static noise margin (SNM), read/write delay, and subthreshold leakage power, are compared with the conventional 6 T SRAM cells. It is reported that the FinFET SRAM cell has RSNM, HSNM, and WNM of 285 mV, 360 mV, and 302 mV, respectively, at Vds = 1 V. Furthermore, the suggested device-based SRAM cell outperforms traditional SRAM cells at 1.0 V in terms of read noise margin, hold noise margin, and write noise margin, as well as leakage power. Thus, it may prove to be a viable option for lowering leakage components, making it effective for low-power and high-performance inverter and SRAM cell design in the nanoscale regime.

A novel design of collapsed supply and boosted bit-line swing write driver for fast write access 9T SRAM

This work presents a collapsed supply and boosted bit-line swing (CSBBS) write driver circuit, with the specific goal of enhancing write performance. The write ability of SRAM cells is gravely affected by device parameter variations in deep sub-threshold region of operations. The collapsed supply and boosted bit-line swing are key features aimed at achieving improvements in speed and efficiency during the memory write process. In comparison to conventional, Ultra dynamic scaled supply write (UDSS), Negative charge-boosted bit line (NCBBL), and Reconfigurable negative bit line collapsed supply (RNBLCS) write driver circuits, Proposed collapsed supply and boosted bit-line swing (CSBBS) for 9T SRAM cell has optimized write access delays of 0.74X, 0.41X, 0.32X and 0.21X, improvement in write margin (WM) of 1.51X, 1.34X, 1.22X and 1.12X respectively. The CSBBS Write driver circuit is implemented using custom compiler (Synopsys) through a 28 nm BSIM4 model card for bulk CMOS. MC simulation results are monitored on Cosmoscope wave viewer (Synopsys).