Subthreshold Model Research Articles

An analytical subthreshold I–V model of SiC MOSFETs

In this article, an analytical I–V model for calculating subthreshold current of SiC MOSFETs is presented. This model starts with planar MOSFETs and utilizes the one-dimensional Poisson’s equation to derive an analytical expression for the surface potential. Subsequently, it employs this expression as a foundation for subthreshold current calculations. Then the model is extended to DMOSFETs based on the fact that channel current formation mechanism of DMOSFETs is similar to that of planar MOSFETs. Comparative analysis of our model calculations with two-dimensional numerical simulation software reveals that our model exhibits a high degree of agreement in the case of planar MOSFETs and DMOSFETs. Interface traps were also considered in our analytical model, which agrees well with experimental data published elsewhere. Furthermore, the model retains a certain degree of accuracy and predictive capability even in the presence of short-channel effect. Our subthreshold model becomes complementary to existing models which only describe the I–V characteristics of SiC MOSFETs when the transistors operate above the threshold voltages.

Analytical Subthreshold Model of Electrical Field-Effect for the Capacitance in Cylindrical Surrounding Double-Gate MOSFET Paradigm

Analytical Subthreshold Model of Electrical Field-Effect for the Capacitance in Cylindrical Surrounding Double-Gate MOSFET Paradigm

Subthreshold model of asymmetric GAA junctionless FETs with scaled equivalent oxide thickness

A comprehensive subthreshold model of asymmetric gate all around (GAA) junctionless (JL) FETs with scaled equivalent oxide thickness is developed in the work. The perimeter weighted sum approach is implemented to model the channel potential and threshold voltage of the device. Further, a novelty in the perimeter weighted approach is proposed to model subthreshold slope of the device. With the proposed novelty appended, the perimeter weighted approach can present a complete subthreshold solution of three dimensional multi-gate devices. Silicon dioxide, Silicon nitride, and stack of Hafnium oxide with interfacial Silicon dioxide are implied as gate dielectric to study the scaling of equivalent oxide thickness of the device in sub-1nm domain. The device characteristics for asymmetric GAA structure imparted due to the dielectric thickness asymmetry have been studied. The numerical results are compared with 3D Sentaurus TCAD device simulation outputs for variation in device parameters.

Novel center potential based analytical sub-threshold model for dual metal broken gate TFET

PurposeThe purpose of this paper is to present an improved model based on center potential instead of surface potential which is physically more relevant and accurate. Also, additional analytic insights have been provided to make the model independent and robust so that it can be extended to a full range compact model.Design/methodology/approachThe design methodology used is center potential based analytical modeling using Psuedo-2D Poisson equation, with ingeniously developed boundary conditions, which help achieve reasonably accurate results. Also, the depletion width calculation has been suitably remodeled, to account for proper physical insights and accuracy.FindingsThe proposed model has considerable accuracy and is able to correctly predict most of the physical phenomena occurring inside the broken gate Tunnel FET structure. Also, a good match has been observed between the modeled data and the simulation results. Ion/Iambipolar ratio of 10^(−8) has been achieved which is quintessential for low power SOCs.Originality/valueThe modeling approach used is different from the previously used techniques and uses indigenous boundary conditions. Also, the current model developed has been significantly altered, using very simple but intuitive technique instead of complex mathematical approach.

Elliptical nanowire FET: Modeling the short-channel subthreshold current caused by interface-trapped-charge and its evaluation for subthreshold logic gate

Based on the quasi-3D potential approach, quasi-3D scaling theory, drift-diffusion model, and equivalent flat-band voltage shift, a short-channel subthreshold current caused by the interface-trapped-charge is modeled for the elliptical nanowire FET. With the subthreshold current, the logic swing (LS) of the subthreshold logic gate composed of elliptical nanowire FET is theoretically evaluated. It indicates that the positive interface-trapped-charge can degrade the high output voltage (V OH ) due to its increased/decreased the subthreshold current of N-FET/P-FET. However, the negative interface-trapped-charge can decrease/increase the subthreshold current of N-FET/P-FET, which hence deteriorates the low output voltage (V OL ). Both degradation of the subthreshold current and LS (i.e., ΔI sub and ΔLS) caused by short-channel effects (SCEs) can be well-controlled by the properly selected scaling factor of α. With the minimum scaling factor, the minimum LS degradation for the subthreshold logic gate can be uniquely determined. • Providing the robust interface-trapped-charged-degraded subthreshold model for the elliptical MOSFET. • Examining how the short-channel-effects together with the interface-trapped-charge-effects affect the logic swing of the subthreshold logic gate.

Novel modification in evanescent mode analysis to incorporate sub-1 nm equivalent oxide thickness in the subthreshold model of junctionless asymmetric double gate FETs

A novel modification in the evanescent mode analysis is presented in this work to comprehend the implication of a high gate dielectric constant in the subthreshold model of junctionless (JL) asymmetric double gate (DG) FETs. A brief study is presented to highlight the lack of an appropriate device model for the JL FET with a sub-1 nm equivalent oxide thickness. This work elaborates the effect of a high-k gate dielectric on one of the most important parameters of evanescent mode analysis, known as the inverse characteristics length. Thereby, an appropriate modification is incorporated in the widely adopted evanescent mode analysis to develop the subthreshold model compatible with high-k gate-dielectric materials and sub-1 nm gate-oxide thickness. Subsequently, the subthreshold model of DG FET with a high-k gate dielectric is presented. The DG FET assumes gate-oxide asymmetry as well as channel doping asymmetry arising due to the ion-implantation and subsequent annealing. With the help of the developed model, the subthreshold characteristics of the device are studied with the variations in device dimensions, the gate-dielectric constant, the doping profile, etc. The results have been found to be in good agreement when numerically studied in comparison with the outcomes of the Synopsys Sentaurus™ Device simulation tool.

Analytical Drain Current and Capacitance Model for Amorphous InGaZnO TFTs Considering Temperature Characteristics

Analytical drain current and capacitance model is developed for the amorphous InGaZnO (a-IGZO) thin-film transistor (TFT). The numerical Pao-Sah model is presented to describe the temperature characteristics considering the deep and tail trap states in the energy gap of the a-IGZO thin film. The numerical model is successful for the TFT in both the subthreshold regime and the above-threshold regime. In the subthreshold regime, considering that the trapped electron concentration in the deep trap states dominates the Poisson's equation, the surface-potential-based analytical model is presented. In the above-threshold regime, the threshold-voltage-based analytical model is presented. Applying the smooth function to connect the subthreshold model and the above-threshold model, the analytical compact model is obtained. The compact model is verified by the numerical Pao-Sah model and the available experimental data from 253 to 393 K. Furthermore, the temperature characteristics of the field-effect mobility are discussed.

Analytical Modeling of Short-Channel Fully-Depleted Triple Work Function Metal Gate (TWFMG) SOI MESFET

In this paper, a new structure: triple work function metal gate SOI MESFET, intended for integration into the deep-submicron CMOS technology, is proposed. The gate of the device consists of three different materials which are laterally merged into one. The difference in the work function of dissimilar gate materials introduces two step changes in the profile of channel potentials which screens the threshold-defining region of the channel from the impact of drain potential. Therefore, the effects associated with DIBL are significantly alleviated. On the basis of exact solution of the Poisson equation in the channel region, an analytical subthreshold model for the device is developed. Using the analytical data, the device has been characterized and compared with conventional device in terms of potential function, DIBL, threshold voltage roll-off, and subthreshold swing. The TCAD simulator ATLAS from Silvaco has been used to validate the analytical results. The feasibility of device fabrication is also demonstrated.

Contact Engineering High-Performance n-Type MoTe2 Transistors.

Semiconducting MoTe2 is one of the few two-dimensional (2D) materials with a moderate band gap, similar to silicon. However, this material remains underexplored for 2D electronics due to ambient instability and predominantly p-type Fermi level pinning at contacts. Here, we demonstrate unipolar n-type MoTe2 transistors with the highest performance to date, including high saturation current (>400 μA/μm at 80 K and >200 μA/μm at 300 K) and relatively low contact resistance (1.2 to 2 kΩ·μm from 80 to 300 K), achieved with Ag contacts and AlOx encapsulation. We also investigate other contact metals (Sc, Ti, Cr, Au, Ni, Pt), extracting their Schottky barrier heights using an analytic subthreshold model. High-resolution X-ray photoelectron spectroscopy reveals that interfacial metal-Te compounds dominate the contact resistance. Among the metals studied, Sc has the lowest work function but is the most reactive, which we counter by inserting monolayer hexagonal boron nitride between MoTe2 and Sc. These metal-insulator-semiconductor (MIS) contacts partly depin the metal Fermi level and lead to the smallest Schottky barrier for electron injection. Overall, this work improves our understanding of n-type contacts to 2D materials, an important advance for low-power electronics.

Investigation of Fin-Width Sensitivity of Threshold Voltage for InGaAs and Si Negative-Capacitance FinFETs Considering Quantum-Confinement Effect

This paper investigates the fin-width ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{W}_{\textsf {Fin}}$ </tex-math></inline-formula> ) sensitivity of threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\textsf {T}}$ </tex-math></inline-formula> ) for InGaAs and Si channel negative-capacitance FinFETs (NC-FinFETs) using a theoretically derived quantum subthreshold model corroborated with TCAD numerical simulation. Our study indicates that due to the action of negative capacitance, the NC-FinFET possesses smaller <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\textsf {T}}$ </tex-math></inline-formula> sensitivity to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{W}_{\textsf {Fin}}$ </tex-math></inline-formula> than the FinFET counterpart. In addition, we point out and demonstrate that a device design with higher internal voltage amplification can be utilized to further reduce the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\textsf {T}}$ </tex-math></inline-formula> sensitivity to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{W}_{\textsf {Fin}}$ </tex-math></inline-formula> for NC-FinFETs. Our study may provide insights for future scaling of FinFETs.

Subthreshold modeling of nanoscale germanium-tin (GeSn)-on-insulator MOSFETs including quantum effects

Although germanium-tin (GeSn) channel p-MOSFETs exhibit outstanding performance compared to other p-MOS transistors, their accurate analytical model has not yet been reported. In this paper, we present, for the first time, a 2-D surface-potential-based sub-threshold model for GeSn-on-insulator (GeSnOI) MOSFETs taking into account the interface-trapped and fixed-oxide charge densities, and also quantum effects. Unlike most of the earlier models applied to elementary and undoped semiconductor channels, the present model embraces variations in the alloy composition as well as doping concentration in the channel. Furthermore the model neither supports iterations nor involves any fitting parameters throughout the derivation, and hence it is physical, predictive, and applicable to circuit simulators like SPICE. We calculate various device parameters such as threshold voltage Vth, threshold voltage roll-up, drain induced barrier lowering DIBL and subthreshold slope SS related to short channel effects (SCEs) of GeSnOI p-MOSFETs for Sn contents ranging 0–6% and channel thickness from 5 to 10 nm. The obtained results show that the GeSnOI MOSFET with channel thickness of 5 nm yields the lowest value of Vth, DIBL, SS and Vth-shift indicating suppression of SCEs. Our model is verified by comparing analytical results for various device parameters with corresponding numerical simulation results and also with limited experimental data available in the literature.

An Analytical Subthreshold Swing Model for fully-depleted MOSFETs with vertical Gaussian profile fabricated on modified silicon-on-insulator wafers

The objective of this study is to present an analytical subthreshold swing model for fully-depleted metal-oxide semiconductor field-effect transistors (MOSFETs) with vertical Gaussian profile fabricated on modified Silicon-on-Insulator (SOI) wafers. Commercial SOI wafers are radiation hardened by Si+ implantation which creates interface traps at buried SiO2/Si interface. Considering that channel potential is affected by non-uniform doping profile combined with process- and radiation-induced traps, the model is derived based on effective conduction path effect. The proposed model is validated by comparing analytical results with numerical simulation data obtained by using commercially available Sentaurus technology computer-aided design. The model agrees well with experimental extractions of irradiated nMOSFETs. This model is believed to be able to provide better physical insight and understanding of total dose irradiated modified SOI MOSFET devices operating in subthreshold regime.

Analytical threshold voltage and subthreshold swing model for TMG FinFET

ABSTRACTAn analytical modelling of the subthreshold surface potential, threshold voltage (VT) and subthreshold swing (SS) for a triple material gate (TMG) FinFET is presented. The basis of the 3D solution is two separate 2D solutions. The FinFET is separated into two 2D structures: asymmetric triple material double gate (TMDG) and symmetric TMDG MOSFETs. Their potential distributions are obtained by solving the corresponding 2D Poisson’s equations. The potential distribution in TMG FinFET is obtained by a parameter-weighted sum of the two 2D solutions. Utilising the concept of minimum source barrier as the leakiest channel path, the minimum value of the surface potential is developed from the potential model. This leads to the derivations for the threshold voltage and SS. Furthermore, the effects of variation in gate work function and gate length are investigated for analytically developed SS and VT models. Our models are validated against TCAD Sentaurus-simulated results and found to be quite accurate.

Short-Channel Effects in 2D Negative-Capacitance Field-Effect Transistors

Through numerical simulations corroborated by an analytical subthreshold model considering drain coupling, this paper systematically investigates the short-channel effects in negative-capacitance FETs with 2D MoS2 channel (2D-NCFET). Our study indicates that, due to the impact of drain coupling on the negative-capacitance effect, the 2D-NCFET exhibits distinct short-channel behaviors such as improved average subthreshold swing and threshold-voltage roll-up with decreasing gate length. In addition, the fringe field through the high-k interlayer dielectric can significantly alter the subthreshold characteristics of the short-channel 2D-NCFET, and hence needs to be carefully taken into account. Our study may provide insights for device design using negative-capacitance FETs.

Analytical Models for the 2DEG Density, AlGaN Layer Carrier Density, and Drain Current for AlGaN/GaN HEMTs

Here, we report a unified analytical model for the 2-D electron gas density ( ${n}_{S}$ ) in AlGaN/GaN HEMTs, considering the carriers induced in the AlGaN layer ( ${n}_{B}$ ) to satisfy charge balance at high gate bias. To extend the validity of our model for gate voltages below the off voltage, we have merged a popular subthreshold model to our model using an interpolation function. Our model for ${n}_{B}$ is fully analytical, without any explicit dependence on ${n}_{S}$ , and is a function only of the gate voltage, which to the best of our knowledge, is the first such report. The model results show a very good match with published results and experimental data reported in the literature. These models are subsequently used in a charge-based drain current model, developed under the drift-diffusion framework. In order to make our model valid for small-dimension devices, several second-order effects have been included in our drain current model. The model results for the drain current show an excellent match with the experimental data reported in the literature, for channel length varying from $1~\mu \text{m}$ to 125 nm. Also, it shows the first-order continuity of the drain current with respect to the bias voltages, thus making it suitable for use in circuit simulators.

Analytical model of nanoscale junctionless transistors towards controlling of short channel effects through source/drain underlap and channel thickness engineering

We develop a 2D analytical subthreshold model for nanoscale double-gate junctionless transistors (DGJLTs) with gate-source/drain underlap. The model is validated using well-calibrated TCAD simulation deck obtained by comparing experimental data in the literature. To analyze and control short-channel effects, we calculate the threshold voltage, drain induced barrier lowering (DIBL) and subthreshold swing of DGJLTs using our model and compare them with corresponding simulation value at channel length of 20 nm with channel thickness tSi ranging 5–10 nm, gate-source/drain underlap (LSD) values 0–7 nm and source/drain doping concentrations (NSD) ranging 5–12 × 1018 cm−3. As tSi reduces from 10 to 5 nm DIBL drops down from 42.5 to 0.42 mV/V at NSD = 1019 cm−3 and LSD = 5 nm in contrast to decrement from 71 to 4.57 mV/V without underlap. For a lower tSiDIBL increases marginally with increasing NSD. The subthreshold swing reduces more rapidly with thinning of channel thickness rather than increasing LSD or decreasing NSD.

Study of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) transistor including source drain depletion length: Model for sub-threshold behavior

The sub-threshold model formulation of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) FET including source/drain depletion length is reported in the present work under the assumption that the ungated regions are fully depleted. To provide deeper insight into the device performance, the impact of gaussian straggle, channel length, oxide and channel thickness and high-k gate dielectric has been studied using extensive TCAD device simulation.

A compact model of organic thin-film transistors for display device

Organic transistor has been widely studied for next generation flexible semiconductor process. In this paper, we proposed the organic thin-film transistors (OTFT) model for the display device at the moderately high temperature (above 273K). The model based on hopping theory of Gaussian disordered density-of-states (DOS) considers the dependences relationship of the carrier mobility with temperature and carrier concentrations. Charge transport is controlled by carrier jumps from trap states around the Fermi level to tail trap states at large carrier concentrations. The sub-threshold model is modified using an exponential function to make the model cover all regimes of OTFT operation. A pentacene-based thin film transistor (TFT) model has been designed using Verilog-A language. The model has been verified by device simulations and measurements.

Subthreshold Slope of Vertical Graphene Interlayer Tunnel Transistor

A subthreshold slope model for the graphene vertical interlayer tunnel transistor is proposed analytically and results are compared and validated from numerical computations. It has been found that irrespective of the energy dependence in computation method, the subthreshold slope of an interlayer tunnel transistor cannot go below the thermionic limit of 60[Formula: see text]mV/decade compared to that of a MOSFET. While thickness of the tunneling barrier, carrier effective mass inside the tunneling barrier, energy band gap between the barrier material and adjacent conductive sandwich layers and the tunneling bias determine the ultimate steepness of the subthreshold slope of such tunnel transistors, a realistic operation of interlayer tunnel transistor at a thin tunnel barrier will always result in a subthreshold slope far greater than the thermionic limit of 60[Formula: see text]mV/decade.

A Compact Subthreshold Model for Short-Channel Monolayer Transition Metal Dichalcogenide Field-Effect Transistors

This brief presents a compact subthreshold model for short-channel monolayer transition metal dichalcogenide (TMD) field-effect transistors. In this model, the impact of fringe fields from the high-K gate dielectric is considered and incorporated into a new characteristic-length expression using a single model parameter. This model has been verified with 2-D numerical simulations for TMD devices with gate length down to 5.9 nm based on ITRS 2028 low-power technology node.