Subexpression Elimination Algorithm Research Articles

A new method for designing multiplierless two-channel filterbank using shifted-Chebyshev polynomials

ABSTRACTThis paper presents an efficient design method for a digital multiplierless two-channel filterbank using the shifted-Chebyshev polynomials and common sub-expression elimination (CSE) algorithm for reducing hardware requirements such as adders and multipliers. For designing a two-channel filterbank, the design problem is constructed as minimization of integral mean square error between the desired and designed response of a prototype filter in the passband and stopband. For controlling the performance in passband and stopband, two parameters (KP, and KS) are used, whose optimum values are determined by swam optimization techniques such as differential evolution algorithm, artificial bee colony optimization, particle swarm optimizations, cuckoo search algorithm and hybrid method using a fitness function, constructed by perfect reconstruction condition of a filterbank. The number of polynomials used for approximation depends upon the order of a prototype filter. A new hybrid CSE is proposed for further reduction of hardware requirement. A comparative study of various CSE techniques such as horizontal, vertical and proposed hybrid CSE is also made. Numerical examples illustrate the effectiveness of the proposed algorithm in the reduction of adders with comparisons accomplished using existing methods. It has been found that almost 43% adder gain can be achieved when a filter is designed with N = 32 and wordlength (WL) as 12 using proposed methodology.

A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical–Horizontal Common Sub-Expression Elimination Algorithm

This paper introduces a computationally efficient hardware architecture for reconfigurable multiple constant multiplication block, which functions according to the canonical signed digit (CSD)-based vertical and horizontal common sub-expression elimination (VHCSE) algorithm. In the proposed architecture, the CSD decoded coefficient along with 4-b common sub-expressions (CSs) in the vertical direction and 4- and 8-b CSs in the horizontal direction reduces the required number of full adder cells and the adder depths. This technique helps in reducing area consumption by decreasing the number of coefficient multiplier adders by 59% than that of the binary VHCSE (VHBCSE) algorithm. This technique helps in reducing the average switching activity of the adder blocks used in each coefficient multiplier block by 26.1%, 25.6%, and 21.3%, while compared with those of the 2- and 3-b binary CS elimination (BCSE) and VHBCSE algorithms, respectively. For different orders of filter, the proposed one delivers 57.5% and 61.9% improvement in area-power product (APP) on an average compared with the VHBCSE and mixed integer programming algorithms, respectively. Experimental results of differently specified finite impulse response (FIR) filters ranging from 10 to 100 taps and the coefficients of 8, 12, and 16 b show the improvements of 42.8%, 53.6%, and 37%, respectively, in the average gate count and 51.8%, 43.5%, and 36.7% less propagation delay than those of earlier canonical double-based number representation method. Moreover, in the metric made of APP divided by throughput, the proposed technique experiences 63.7% improvement on an average over that of faithfully rounded truncated multiple constant multiplication/accumulation technique of designing constant multiplier and demonstrates its suitability for implementing efficient reconfigurable FIR filter.

Performance of CSE Techniques for Designing Multiplier-Less FIR Filter Using Evolutionary Algorithms

In this work, an efficient design of multiplier-less digital finite impulse response (FIR) filter is presented, where the sub-expression elimination (SE) algorithms are employed on filter coefficients, and optimization is done with evolutionary algorithms. This FIR filter is designed with novelty of optimizing the quantized coefficients inside each of the respective optimization algorithm, instead of using two separate algorithms: one for generation of optimal continuous coefficients, and second for optimizing the quantized coefficients. Comparative analysis using different SE techniques have been utilized for reducing the requirement of adders on both binary represented and canonic signed digit converted filter coefficients. The simulation results illustrate the impact of proposed algorithm along with significant reduction in number of adders.

Enhanced MixColumn Design for AES Encryption

The main aim of the current research work is to reduce the complexity path of AES (Advanced Encryption Standard) Encryption. Architecture of MixColumn transformation has been optimized in this research work. Traditional methods of MixColumn transformation methods has been realized and re-designed by reducing the redundant logical functions. Verilog Hardware Description Language (Verilog HDL) has been used to design the optimized MixColumn transformation of AES Encryption. Further optimized MixColumn design has been incorporated into AES Encryption with appropriate input points. Common Sub-expression Elimination (CSE) algorithm is used in developed AES Encryption algorithm. Proposed optimized MixColumn design offers 10.93% improvements in hardware slices, 13.6% improvements in LUTs and 1.19% improvements in delay consumption than traditional MixColumn design. Further proposed optimized MixColumn design has been incorporated into AES Encryption design. Further, proposed optimized MixColumn based AES Encryption design offers 4.75% improvements in silicon area, 4.56% reduction in power consumption than traditional MixColumn based AES Encryption. In future, proposed optimized MixColumn design will be useful in space and terrestrial applications for exhibiting secure transmissions.

Design of High-Order Extrapolated Impulse Response FIR Filters with Signed Powers-of-Two Coefficients

Expensive multiplication operations can be replaced by simpler additions and hardwired shifters so as to reduce power consumption and area size, if the coefficients of a digital filter are signed power-of-two (SPT). As a consequence, FIR digital filters with SPT coefficients have been widely studied in the last three decades. However, most approaches for the design of FIR filters with SPT coefficients focus on filters with length less than 100. These approaches are not suitable for the design of high-order filters because they require excessive computation time. In this paper, an approach for the design of high-order filters with SPT coefficients is proposed. It is a two-step approach. Firstly, the design of an extrapolated impulse response (EIR) filter is formulated as a standard second-order cone programming (SOCP) problem with an additional coefficient sensitivity constraint for optimizing its finite word-length effect. Secondly, the obtained continuous coefficients are quantized into SPT coefficients by recasting the filter-design problem into a weighted least squares (WLS) sequential quadratic programming relaxation (SQPR) problem. To further reduce implementation complexity, a graph-based common subexpression elimination (CSE) algorithm is utilized to extract common subexpressions between SPT coefficients. Simulation results show that the proposed method can effectively and efficiently design high-order SPT filters, including Hilbert transformers and half-band filters with SPT coefficients. Experiment results indicate that 0.81N∼0.29N adders are required for 18-bit N-order FIR filters (N=335∼3261) to meet the given magnitude response specifications.

Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs

We present a method for implementing high speed finite impulse response (FIR) filters on field programmable gate arrays (FPGAs). Our algorithm is a multiplierless technique where fixed coefficient multipliers are replaced with a series of add and shift operations. The first phase of our algorithm uses registered adders and hardwired shifts. Here, a modified common subexpression elimination (CSE) algorithm reduces the number of adders while maintaining performance. The second phase optimizes routing delay using prelayout wire length estimation techniques to improve the final placed and routed design. The optimization target platforms are Xilinx Virtex FPGA devices where we compare the implementation results with those produced by Xilinx Coregen, which is based on distributed arithmetic (DA). We observed up to 50% reduction in the number of slices and up to 75% reduction in the number of look up tables (LUTs) for fully parallel implementations compared to DA method. Also, there is 50% reduction in the total dynamic power consumption of the filters. Our designs perform up to 27% faster than the multiply accumulate (MAC) filters implemented by Xilinx Coregen tool using DSP blocks. For placement, there is a saving up to 20% in number of routing channels. This results in lower congestion and up to 8% reduction in average wirelength.